davids5 commented on pull request #3525: URL: https://github.com/apache/incubator-nuttx/pull/3525#issuecomment-817763746
> For some reason (which I didn't fully understand), setting the MPU_RASR_S makes SRAM not writable. Not setting this bit solves the problem; My thinking here is that since this is a single core chip anyhow, it is fine to leave the bit out. @jlaitine Is this the reason? The S field is for a shareable memory region: the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. A strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, the software must ensure the data coherency between the bus masters. **The STM32F7 Series and STM32H7 Series do not support hardware coherency. The S field is equivalent to non-cacheable memory**. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: [email protected]
