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commit 534c058d934e8fe043959c6e28be318573dc819e Author: Gustavo Henrique Nihei <[email protected]> AuthorDate: Wed May 5 15:03:23 2021 -0300 spi: Adopt CPHA as the abbreviation for clock phase --- arch/arm/src/imx1/imx_spi.c | 8 ++++---- arch/arm/src/imx6/imx_ecspi.c | 8 ++++---- arch/arm/src/tiva/common/tiva_ssi.c | 8 ++++---- arch/renesas/src/rx65n/rx65n_rspi.c | 8 ++++---- arch/renesas/src/rx65n/rx65n_rspi_sw.c | 8 ++++---- arch/z80/src/ez80/ez80_spi.c | 8 ++++---- boards/arm/stm32f7/nucleo-144/Kconfig | 24 ++++++++++++------------ include/nuttx/spi/qspi.h | 8 ++++---- include/nuttx/spi/slave.h | 8 ++++---- include/nuttx/spi/spi.h | 8 ++++---- 10 files changed, 48 insertions(+), 48 deletions(-) diff --git a/arch/arm/src/imx1/imx_spi.c b/arch/arm/src/imx1/imx_spi.c index 6719c61..d345b6b 100644 --- a/arch/arm/src/imx1/imx_spi.c +++ b/arch/arm/src/imx1/imx_spi.c @@ -826,19 +826,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = CSPI_CTRL_PHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = CSPI_CTRL_POL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = CSPI_CTRL_PHA | CSPI_CTRL_POL; break; diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c index 2f77640..0e0d166 100644 --- a/arch/arm/src/imx6/imx_ecspi.c +++ b/arch/arm/src/imx6/imx_ecspi.c @@ -929,19 +929,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = ECSPI_CONREG_PHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = ECSPI_CONREG_POL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = ECSPI_CONREG_PHA | ECSPI_CONREG_POL; break; diff --git a/arch/arm/src/tiva/common/tiva_ssi.c b/arch/arm/src/tiva/common/tiva_ssi.c index a0cd295..374801b 100644 --- a/arch/arm/src/tiva/common/tiva_ssi.c +++ b/arch/arm/src/tiva/common/tiva_ssi.c @@ -1250,19 +1250,19 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv, switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = SSI_CR0_SPH; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = SSI_CR0_SPO; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = SSI_CR0_SPH | SSI_CR0_SPO; break; diff --git a/arch/renesas/src/rx65n/rx65n_rspi.c b/arch/renesas/src/rx65n/rx65n_rspi.c index e91c77f..06076bc 100644 --- a/arch/renesas/src/rx65n/rx65n_rspi.c +++ b/arch/renesas/src/rx65n/rx65n_rspi.c @@ -1841,19 +1841,19 @@ static void rspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = RSPI_SPCMD_PHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = RSPI_SPCMD_POL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = RSPI_SPCMD_PHA | RSPI_SPCMD_POL; break; diff --git a/arch/renesas/src/rx65n/rx65n_rspi_sw.c b/arch/renesas/src/rx65n/rx65n_rspi_sw.c index b530043..09cbb5d 100644 --- a/arch/renesas/src/rx65n/rx65n_rspi_sw.c +++ b/arch/renesas/src/rx65n/rx65n_rspi_sw.c @@ -1476,19 +1476,19 @@ static void rspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = RSPI_SPCMD_PHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = RSPI_SPCMD_POL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = RSPI_SPCMD_PHA | RSPI_SPCMD_POL; break; diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c index aaedd87..90976cf 100644 --- a/arch/z80/src/ez80/ez80_spi.c +++ b/arch/z80/src/ez80/ez80_spi.c @@ -274,19 +274,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) switch (mode) { - case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + case SPIDEV_MODE0: /* CPOL=0 CPHA=0 */ modebits = 0; break; - case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + case SPIDEV_MODE1: /* CPOL=0 CPHA=1 */ modebits = SPI_CTL_CPHA; break; - case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + case SPIDEV_MODE2: /* CPOL=1 CPHA=0 */ modebits = SPI_CTL_CPOL; break; - case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + case SPIDEV_MODE3: /* CPOL=1 CPHA=1 */ modebits = (SPI_CTL_CPOL | SPI_CTL_CPHA); break; diff --git a/boards/arm/stm32f7/nucleo-144/Kconfig b/boards/arm/stm32f7/nucleo-144/Kconfig index e0d39ab..8128871 100644 --- a/boards/arm/stm32f7/nucleo-144/Kconfig +++ b/boards/arm/stm32f7/nucleo-144/Kconfig @@ -154,16 +154,16 @@ choice Sets SPI 1 clock mode config NUCLEO_SPI1_TEST_MODE0 - bool "CPOL=0 CHPHA=0" + bool "CPOL=0 CPHA=0" config NUCLEO_SPI1_TEST_MODE1 - bool "CPOL=0 CHPHA=1" + bool "CPOL=0 CPHA=1" config NUCLEO_SPI1_TEST_MODE2 - bool "CPOL=1 CHPHA=0" + bool "CPOL=1 CPHA=0" config NUCLEO_SPI1_TEST_MODE3 - bool "CPOL=1 CHPHA=1" + bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 1 Clock Mode" @@ -199,16 +199,16 @@ choice Sets SPI 2 clock mode config NUCLEO_SPI2_TEST_MODE0 - bool "CPOL=0 CHPHA=0" + bool "CPOL=0 CPHA=0" config NUCLEO_SPI2_TEST_MODE1 - bool "CPOL=0 CHPHA=1" + bool "CPOL=0 CPHA=1" config NUCLEO_SPI2_TEST_MODE2 - bool "CPOL=1 CHPHA=0" + bool "CPOL=1 CPHA=0" config NUCLEO_SPI2_TEST_MODE3 - bool "CPOL=1 CHPHA=1" + bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 2 Clock Mode" @@ -244,16 +244,16 @@ choice Sets SPI 3 clock mode config NUCLEO_SPI3_TEST_MODE0 - bool "CPOL=0 CHPHA=0" + bool "CPOL=0 CPHA=0" config NUCLEO_SPI3_TEST_MODE1 - bool "CPOL=0 CHPHA=1" + bool "CPOL=0 CPHA=1" config NUCLEO_SPI3_TEST_MODE2 - bool "CPOL=1 CHPHA=0" + bool "CPOL=1 CPHA=0" config NUCLEO_SPI3_TEST_MODE3 - bool "CPOL=1 CHPHA=1" + bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 3 Clock Mode" diff --git a/include/nuttx/spi/qspi.h b/include/nuttx/spi/qspi.h index f3cb27d..51c9547 100644 --- a/include/nuttx/spi/qspi.h +++ b/include/nuttx/spi/qspi.h @@ -228,10 +228,10 @@ enum qspi_mode_e { - QSPIDEV_MODE0 = 0, /* CPOL=0 CHPHA=0 */ - QSPIDEV_MODE1, /* CPOL=0 CHPHA=1 */ - QSPIDEV_MODE2, /* CPOL=1 CHPHA=0 */ - QSPIDEV_MODE3 /* CPOL=1 CHPHA=1 */ + QSPIDEV_MODE0 = 0, /* CPOL=0 CPHA=0 */ + QSPIDEV_MODE1, /* CPOL=0 CPHA=1 */ + QSPIDEV_MODE2, /* CPOL=1 CPHA=0 */ + QSPIDEV_MODE3 /* CPOL=1 CPHA=1 */ }; /* This structure describes one command transfer */ diff --git a/include/nuttx/spi/slave.h b/include/nuttx/spi/slave.h index c6fa92c..3f8b70b 100644 --- a/include/nuttx/spi/slave.h +++ b/include/nuttx/spi/slave.h @@ -467,10 +467,10 @@ enum spi_smode_e { - SPISLAVE_MODE0 = 0, /* CPOL=0 CHPHA=0 */ - SPISLAVE_MODE1, /* CPOL=0 CHPHA=1 */ - SPISLAVE_MODE2, /* CPOL=1 CHPHA=0 */ - SPISLAVE_MODE3 /* CPOL=1 CHPHA=1 */ + SPISLAVE_MODE0 = 0, /* CPOL=0 CPHA=0 */ + SPISLAVE_MODE1, /* CPOL=0 CPHA=1 */ + SPISLAVE_MODE2, /* CPOL=1 CPHA=0 */ + SPISLAVE_MODE3 /* CPOL=1 CPHA=1 */ }; /* The SPI slave controller driver vtable */ diff --git a/include/nuttx/spi/spi.h b/include/nuttx/spi/spi.h index 18d4506..7765050 100644 --- a/include/nuttx/spi/spi.h +++ b/include/nuttx/spi/spi.h @@ -521,10 +521,10 @@ enum spi_devtype_e enum spi_mode_e { - SPIDEV_MODE0 = 0, /* CPOL=0 CHPHA=0 */ - SPIDEV_MODE1, /* CPOL=0 CHPHA=1 */ - SPIDEV_MODE2, /* CPOL=1 CHPHA=0 */ - SPIDEV_MODE3, /* CPOL=1 CHPHA=1 */ + SPIDEV_MODE0 = 0, /* CPOL=0 CPHA=0 */ + SPIDEV_MODE1, /* CPOL=0 CPHA=1 */ + SPIDEV_MODE2, /* CPOL=1 CPHA=0 */ + SPIDEV_MODE3, /* CPOL=1 CPHA=1 */ SPIDEV_MODETI, /* CPOL=0 CPHA=1 TI Synchronous Serial Frame Format */ };
