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commit 2a21c45e0a24c19b47543d38010404dfe33aab8d Author: Daniel P. Carvalho <[email protected]> AuthorDate: Wed Jul 7 14:59:12 2021 -0300 Add STM32G43XX Analog Comparator driver. --- arch/arm/src/stm32/Kconfig | 404 +++++++++- arch/arm/src/stm32/hardware/stm32_comp.h | 6 + arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h | 22 +- arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h | 167 ++++ arch/arm/src/stm32/stm32_comp.c | 14 + arch/arm/src/stm32/stm32_comp.h | 121 +-- arch/arm/src/stm32/stm32_comp_v1.c | 21 +- .../src/stm32/{stm32_comp.h => stm32_comp_v1.h} | 53 +- .../src/stm32/{stm32_comp_v1.c => stm32_comp_v2.c} | 859 ++++++++++----------- arch/arm/src/stm32/stm32_comp_v2.h | 97 +++ 10 files changed, 1113 insertions(+), 651 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 0e53027..64da99a 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1933,6 +1933,7 @@ config STM32_STM32G4XXX select STM32_HAVE_DMAMUX select STM32_HAVE_IP_DBGMCU_V3 select STM32_HAVE_IP_ADC_V2 + select STM32_HAVE_IP_COMP_V2 select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V2 select STM32_HAVE_IP_TIMERS_V3 @@ -2621,6 +2622,10 @@ config STM32_HAVE_IP_COMP_V1 bool default n +config STM32_HAVE_IP_COMP_V2 + bool + default n + # These are the peripheral selections proper config STM32_ADC1 @@ -3352,7 +3357,7 @@ config STM32_PWM config STM32_COMP bool default n - depends on STM32_STM32L15XX || STM32_STM32F33XX + depends on STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX config STM32_OPAMP bool @@ -8505,6 +8510,403 @@ config STM32_ADC5_JEXTSEL endmenu +menu "COMP Configuration" + depends on STM32_COMP && STM32_HAVE_IP_COMP_V2 + +config STM32_COMP1_OUT + bool "COMP1 GPIO Output" + depends on STM32_COMP1 + default n + ---help--- + Enables COMP1 output. + +config STM32_COMP1_INM + int "COMP1 inverting input assignment" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects COMP1 inverting input pin. + +config STM32_COMP1_INP + int "COMP1 non-inverting input assignment" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 non-inverting input pin. + +config STM32_COMP1_POL + int "COMP1 polarity" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 output polarity. + +config STM32_COMP1_HYST + int "COMP1 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP1. + +config STM32_COMP1_BLANKSEL + int "COMP1 blanking signal select" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP1. + +config STM32_COMP1_LOCK + int "COMP1 COMP_CxCSR register lock" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP2_OUT + bool "COMP2 GPIO Output" + depends on STM32_COMP2 + default n + ---help--- + Enables COMP2 output. + +config STM32_COMP2_INM + int "COMP2 inverting input assignment" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects COMP2 inverting input pin. + +config STM32_COMP2_INP + int "COMP2 non-inverting input assignment" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Selects COMP2 non-inverting input pin. + +config STM32_COMP2_POL + int "COMP2 polarity" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Selects COMP2 output polarity. + +config STM32_COMP2_HYST + int "COMP2 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP2. + +config STM32_COMP2_BLANKSEL + int "COMP2 blanking signal select" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP2. + +config STM32_COMP2_LOCK + int "COMP2 COMP_CxCSR register lock" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP3_OUT + bool "COMP3 GPIO Output" + depends on STM32_COMP3 + default n + ---help--- + Enables COMP3 output. + +config STM32_COMP3_INM + int "COMP3 inverting input assignment" + depends on STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects COMP3 inverting input pin. + +config STM32_COMP3_INP + int "COMP3 non-inverting input assignment" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 non-inverting input pin. + +config STM32_COMP3_POL + int "COMP3 polarity" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 output polarity. + +config STM32_COMP3_HYST + int "COMP3 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP3. + +config STM32_COMP3_BLANKSEL + int "COMP3 blanking signal select" + depends on STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP3. + +config STM32_COMP3_LOCK + int "COMP3 COMP_CxCSR register lock" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP4_OUT + bool "COMP4 GPIO Output" + depends on STM32_COMP4 + default n + ---help--- + Enables COMP4 output. + +config STM32_COMP4_INM + int "COMP4 inverting input assignment" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects COMP4 inverting input pin. + +config STM32_COMP4_INP + int "COMP4 non-inverting input assignment" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Selects COMP4 non-inverting input pin. + +config STM32_COMP4_POL + int "COMP4 polarity" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Selects COMP4 output polarity. + +config STM32_COMP4_HYST + int "COMP4 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP4. + +config STM32_COMP4_BLANKSEL + int "COMP4 blanking signal select" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP4. + +config STM32_COMP4_LOCK + int "COMP4 COMP_CxCSR register lock" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP5_OUT + bool "COMP5 GPIO Output" + depends on STM32_COMP5 + default n + ---help--- + Enables COMP5 output. + +config STM32_COMP5_INM + int "COMP5 inverting input assignment" + depends on STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects COMP5 inverting input pin. + +config STM32_COMP5_INP + int "COMP5 non-inverting input assignment" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Selects COMP5 non-inverting input pin. + +config STM32_COMP5_POL + int "COMP5 polarity" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Selects COMP5 output polarity. + +config STM32_COMP5_HYST + int "COMP5 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP5. + +config STM32_COMP5_BLANKSEL + int "COMP5 blanking signal select" + depends on STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP5. + +config STM32_COMP5_LOCK + int "COMP5 COMP_CxCSR register lock" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP6_OUT + bool "COMP6 GPIO Output" + depends on STM32_COMP6 + default n + ---help--- + Enables COMP6 output. + +config STM32_COMP6_INM + int "COMP6 inverting input assignment" + depends on STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects COMP6 inverting input pin. + +config STM32_COMP6_INP + int "COMP6 non-inverting input assignment" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Selects COMP6 non-inverting input pin. + +config STM32_COMP6_POL + int "COMP6 polarity" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Selects COMP6 output polarity. + +config STM32_COMP6_HYST + int "COMP6 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP6. + +config STM32_COMP6_BLANKSEL + int "COMP6 blanking signal select" + depends on STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP6. + +config STM32_COMP6_LOCK + int "COMP6 COMP_CxCSR register lock" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP7_OUT + bool "COMP7 GPIO Output" + depends on STM32_COMP7 + default n + ---help--- + Enables COMP7 output. + +config STM32_COMP7_INM + int "COMP7 inverting input assignment" + depends on STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects COMP7 inverting input pin. + +config STM32_COMP7_INP + int "COMP7 non-inverting input assignment" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Selects COMP7 non-inverting input pin. + +config STM32_COMP7_POL + int "COMP7 polarity" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Selects COMP7 output polarity. + +config STM32_COMP7_HYST + int "COMP7 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP7. + +config STM32_COMP7_BLANKSEL + int "COMP7 blanking signal select" + depends on STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP7. + +config STM32_COMP7_LOCK + int "COMP7 COMP_CxCSR register lock" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endmenu + menu "SDADC Configuration" depends on STM32_SDADC diff --git a/arch/arm/src/stm32/hardware/stm32_comp.h b/arch/arm/src/stm32/hardware/stm32_comp.h index b9f6903..ec00744 100644 --- a/arch/arm/src/stm32/hardware/stm32_comp.h +++ b/arch/arm/src/stm32/hardware/stm32_comp.h @@ -43,6 +43,12 @@ # else # error "Device not supported." # endif +#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +# if defined(CONFIG_STM32_STM32G4XXX) +# include "stm32g4xxxx_comp.h" +# else +# error "Device not supported." +# endif #else # error "STM32 COMP IP not supported." #endif diff --git a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h b/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h index b7ba8df..0cf23f8 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h @@ -65,6 +65,8 @@ /* COMP - Comparator ********************************************************/ +/* Comparator Outputs */ + #define GPIO_COMP1_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN0) #define GPIO_COMP1_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN6) #define GPIO_COMP1_OUT_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN11) @@ -74,9 +76,25 @@ #define GPIO_COMP2_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN7) #define GPIO_COMP2_OUT_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN12) -#define GPIO_COMP3_OUT (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_COMP3_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN7) + +#define GPIO_COMP4_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN6) + +/* Comparator Inputs non inverting */ + +#define GPIO_COMP1_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_COMP1_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) + +#define GPIO_COMP2_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_COMP2_INP_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) + +/* Comparator Inputs non inverting */ + +#define GPIO_COMP1_INM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_COMP1_INM_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) -#define GPIO_COMP4_OUT (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_COMP2_INM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_COMP2_INM_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) /* DAC **********************************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h b/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h new file mode 100644 index 0000000..51d37fe --- /dev/null +++ b/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h @@ -0,0 +1,167 @@ +/**************************************************************************** + * arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_COMP_H +#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_COMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +#define STM32_COMP1_CSR STM32_COMP1_BASE +#define STM32_COMP2_CSR STM32_COMP2_BASE +#define STM32_COMP3_CSR STM32_COMP3_BASE +#define STM32_COMP4_CSR STM32_COMP4_BASE +#define STM32_COMP5_CSR STM32_COMP5_BASE +#define STM32_COMP6_CSR STM32_COMP6_BASE +#define STM32_COMP7_CSR STM32_COMP7_BASE + +/* Register Bitfield Definitions ********************************************/ + +/* COMP control and status register */ + +#define COMP_CSR_COMPEN (1 << 0) /* Bit 0: Comparator enable */ + /* Bits 3-1: Reserved */ +#define COMP_CSR_INMSEL_SHIFT (4) /* Bits 7-4: Comparator inverting input selection */ +#define COMP_CSR_INMSEL_MASK (15 << COMP_CSR_INMSEL_SHIFT) +# define COMP_CSR_INMSEL_1P4VREF (0 << COMP_CSR_INMSEL_SHIFT) /* 0000: 1/4 of Vrefint */ +# define COMP_CSR_INMSEL_1P2VREF (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: 1/2 of Vrefint */ +# define COMP_CSR_INMSEL_3P4VREF (2 << COMP_CSR_INMSEL_SHIFT) /* 0010: 3/4 of Vrefint */ +# define COMP_CSR_INMSEL_VREF (3 << COMP_CSR_INMSEL_SHIFT) /* 0011: Vrefint */ +# define COMP_CSR_INMSEL_DAC3CH1 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC3_CH1 (COMP1 and COMP3 only) */ +# define COMP_CSR_INMSEL_DAC3CH2 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC3_CH2 (COMP2 and COMP4 only) */ +# define COMP_CSR_INMSEL_DAC4CH1 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC4_CH1 (COMP5 and COMP7 only) */ +# define COMP_CSR_INMSEL_DAC4CH2 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC4_CH2 (COMP6 only) */ +# define COMP_CSR_INMSEL_DAC1CH1 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC1_CH1 (COMP1, COMP3 and COMP4 only) */ +# define COMP_CSR_INMSEL_DAC1CH2 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC1_CH2 (COMP2 and COMP5 only) */ +# define COMP_CSR_INMSEL_DAC2CH1 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC2_CH1 (COMP6 and COMP7 only) */ +# define COMP_CSR_INMSEL_PA4 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PA4 (COMP1 only) */ +# define COMP_CSR_INMSEL_PA5 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PA5 (COMP2 only) */ +# define COMP_CSR_INMSEL_PF1 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PF1 (COMP3 only) */ +# define COMP_CSR_INMSEL_PE8 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PE8 (COMP4 only) */ +# define COMP_CSR_INMSEL_PB10 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PB10 (COMP5 only) */ +# define COMP_CSR_INMSEL_PD10 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PD10 (COMP6 only) */ +# define COMP_CSR_INMSEL_PD15 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PD15 (COMP7 only) */ +# define COMP_CSR_INMSEL_PA0 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PA0 (COMP1 only) */ +# define COMP_CSR_INMSEL_PA2 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PA2 (COMP2 only) */ +# define COMP_CSR_INMSEL_PC0 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PC0 (COMP3 only) */ +# define COMP_CSR_INMSEL_PB2 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */ +# define COMP_CSR_INMSEL_PD13 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PD13 (COMP5 only) */ +# define COMP_CSR_INMSEL_PB15 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB15 (COMP6 only) */ +# define COMP_CSR_INMSEL_PB12 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB12 (COMP7 only) */ + +#define COMP_CSR_INPSEL_SHIFT (8) /* Bit 8: Comparator non-inverting input selection */ +# define COMP_CSR_INPSEL_PA1 (0 << COMP_CSR_INPSEL_SHIFT) /* PA1 (COMP1 only) */ +# define COMP_CSR_INPSEL_PB1 (1 << COMP_CSR_INPSEL_SHIFT) /* PB1 (COMP1 only) */ +# define COMP_CSR_INPSEL_PA7 (0 << COMP_CSR_INPSEL_SHIFT) /* PA7 (COMP2 only) */ +# define COMP_CSR_INPSEL_PA3 (1 << COMP_CSR_INPSEL_SHIFT) /* PA3 (COMP2 only) */ +# define COMP_CSR_INPSEL_PA0 (0 << COMP_CSR_INPSEL_SHIFT) /* PA0 (COMP3 only) */ +# define COMP_CSR_INPSEL_PC1 (1 << COMP_CSR_INPSEL_SHIFT) /* PC1 (COMP3 only) */ +# define COMP_CSR_INPSEL_PB0 (0 << COMP_CSR_INPSEL_SHIFT) /* PB0 (COMP4 only) */ +# define COMP_CSR_INPSEL_PE7 (1 << COMP_CSR_INPSEL_SHIFT) /* PE7 (COMP4 only) */ +# define COMP_CSR_INPSEL_PB13 (0 << COMP_CSR_INPSEL_SHIFT) /* PB13 (COMP5 only) */ +# define COMP_CSR_INPSEL_PD12 (1 << COMP_CSR_INPSEL_SHIFT) /* PD12 (COMP5 only) */ +# define COMP_CSR_INPSEL_PB11 (0 << COMP_CSR_INPSEL_SHIFT) /* PB11 (COMP6 only) */ +# define COMP_CSR_INPSEL_PD11 (1 << COMP_CSR_INPSEL_SHIFT) /* PD11 (COMP6 only) */ +# define COMP_CSR_INPSEL_PB14 (0 << COMP_CSR_INPSEL_SHIFT) /* PB14 (COMP7 only) */ +# define COMP_CSR_INPSEL_PD14 (1 << COMP_CSR_INPSEL_SHIFT) /* PD14 (COMP7 only) */ + /* Bits 14-9: Reserved */ +#define COMP_CSR_POL (1 << 15) /* Bit 15: comparator output polarity */ + +#define COMP_CSR_HYST_SHIFT (16) /* Bits 18-16: Comparator hysteresis */ +#define COMP_CSR_HYST_MASK (7 << COMP_CSR_HYST_SHIFT) +# define COMP_CSR_HYST_0MV (0 << COMP_CSR_HYST_SHIFT) /* No hysteresis */ +# define COMP_CSR_HYST_10MV (1 << COMP_CSR_HYST_SHIFT) /* 10mV hysteresis */ +# define COMP_CSR_HYST_20MV (2 << COMP_CSR_HYST_SHIFT) /* 20mV hysteresis */ +# define COMP_CSR_HYST_30MV (3 << COMP_CSR_HYST_SHIFT) /* 30mV hysteresis */ +# define COMP_CSR_HYST_40MV (4 << COMP_CSR_HYST_SHIFT) /* 40mV hysteresis */ +# define COMP_CSR_HYST_50MV (5 << COMP_CSR_HYST_SHIFT) /* 50mV hysteresis */ +# define COMP_CSR_HYST_60MV (6 << COMP_CSR_HYST_SHIFT) /* 60mV hysteresis */ +# define COMP_CSR_HYST_70MV (7 << COMP_CSR_HYST_SHIFT) /* 70mV hysteresis */ + +#define COMP_CSR_BLANKING_SHIFT (19) /* Bit 21-19: Comparator blanking signal select */ +#define COMP_CSR_BLANKING_MASK (7 << COMP_CSR_BLANKING_SHIFT) +# define COMP_CSR_BLANKING_DIS (0 << COMP_CSR_BLANKING_SHIFT) /* 000: No blanking */ +# define COMP1_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1_OC5 */ +# define COMP2_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1_OC5 */ +# define COMP3_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1_OC5 */ +# define COMP4_CSR_BLANKING_T3OC4 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM3_OC4 */ +# define COMP5_CSR_BLANKING_T2OC3 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM2_OC3 */ +# define COMP6_CSR_BLANKING_T8OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM8_OC5 */ +# define COMP7_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1_OC5 */ +# define COMP1_CSR_BLANKING_T2OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2_OC3 */ +# define COMP2_CSR_BLANKING_T2OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2_OC3 */ +# define COMP3_CSR_BLANKING_T3OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM3_OC3 */ +# define COMP4_CSR_BLANKING_T8OC5 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM8_OC5 */ +# define COMP5_CSR_BLANKING_T8OC5 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM8_OC5 */ +# define COMP6_CSR_BLANKING_T2OC4 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2_OC4 */ +# define COMP7_CSR_BLANKING_T8OC5 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM8_OC5 */ +# define COMP1_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3_OC3 */ +# define COMP2_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3_OC3 */ +# define COMP3_CSR_BLANKING_T2OC4 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM2_OC4 */ +# define COMP4_CSR_BLANKING_T15OC1 (3 << COMP_CSR_BLANKING_SHIFT) /* 011 or 110: TIM15_OC1 */ +# define COMP5_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3_OC3 */ +# define COMP6_CSR_BLANKING_T15OC2 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM15_OC2 */ +# define COMP7_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3_OC3 */ +# define COMP1_CSR_BLANKING_T8OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM8_OC5 */ +# define COMP2_CSR_BLANKING_T8OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM8_OC5 */ +# define COMP3_CSR_BLANKING_T8OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM8_OC5 */ +# define COMP4_CSR_BLANKING_T1OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM1_OC5 */ +# define COMP5_CSR_BLANKING_T1OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM1_OC5 */ +# define COMP6_CSR_BLANKING_T1OC5 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM1_OC5 */ +# define COMP7_CSR_BLANKING_T15OC2 (4 << COMP_CSR_BLANKING_SHIFT) /* 100: TIM15_OC2 */ +# define COMP1_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP2_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP3_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP4_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP5_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP6_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP7_CSR_BLANKING_T20OC5 (5 << COMP_CSR_BLANKING_SHIFT) /* 101: TIM20_OC5 */ +# define COMP1_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP2_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP3_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP5_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP6_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP7_CSR_BLANKING_T15OC1 (6 << COMP_CSR_BLANKING_SHIFT) /* 110: TIM15_OC1 */ +# define COMP1_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP2_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP3_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP4_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP5_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP6_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ +# define COMP7_CSR_BLANKING_T4OC3 (6 << COMP_CSR_BLANKING_SHIFT) /* 111: TIM4_OC3 */ + +#define COMP_CSR_BRGEN (1 << 22) /* Bit 22: Scaler resistor bridge enable */ +#define COMP_CSR_SCALEN (1 << 23) /* Bit 22: scaler enable */ + /* Bits 29-24: Reserved */ +#define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status */ +#define COMP_CSR_LOCK (1 << 31) /* Bit 31: Register lock */ + +#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_COMP_H */ diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c index 38f31a5..b34545f 100644 --- a/arch/arm/src/stm32/stm32_comp.c +++ b/arch/arm/src/stm32/stm32_comp.c @@ -24,7 +24,19 @@ #include <nuttx/config.h> +#include <stdint.h> +#include <errno.h> +#include <assert.h> +#include <debug.h> + +#include <arch/board/board.h> +#include <nuttx/analog/comp.h> +#include <nuttx/analog/ioctl.h> + +#include "arm_arch.h" #include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" /* This file is only a thin shell that includes the correct COMP * implementation. At this moment only STM32 COMP IP version 1 device is @@ -34,6 +46,8 @@ #if defined(CONFIG_STM32_HAVE_IP_COMP_V1) # include "stm32_comp_v1.c" +#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +# include "stm32_comp_v2.c" #else # error "STM32 COMP IP version not supported." #endif diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h index 1212911..21ab266 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/stm32/stm32_comp.h @@ -31,128 +31,20 @@ #include "hardware/stm32_comp.h" -#ifdef CONFIG_STM32_COMP +#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +# include "stm32_comp_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +# include "stm32_comp_v2.h" +#endif /**************************************************************************** * Pre-processor definitions ****************************************************************************/ -#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */ -#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */ -#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */ -#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */ -#define COMP_LOCK_DEFAULT COMP_LOCK_RW /* Do not lock CSR register */ - -#ifndef CONFIG_STM32_STM32F33XX -#define COMP_MODE_DEFAULT -#define COMP_HYST_DEFAULT -#define COMP_WINMODE_DEFAULT -#endif - /**************************************************************************** * Public Types ****************************************************************************/ -/* Blanking source */ - -enum stm32_comp_blanking_e -{ - COMP_BLANKING_DIS, -#if defined(CONFIG_STM32_STM32F33XX) - COMP_BLANKING_T1OC5, - COMP_BLANKING_T3OC4, - COMP_BLANKING_T2OC3, - COMP_BLANKING_T3OC3, - COMP_BLANKING_T15OC1, - COMP_BLANKING_T2OC4, - COMP_BLANKING_T15OC2, -#endif -}; - -/* Output polarisation */ - -enum stm32_comp_pol_e -{ - COMP_POL_NONINVERT, - COMP_POL_INVERTED -}; - -/* Inverting input */ - -enum stm32_comp_inm_e -{ - COMP_INMSEL_1P4VREF, - COMP_INMSEL_1P2VREF, - COMP_INMSEL_3P4VREF, - COMP_INMSEL_VREF, - COMP_INMSEL_DAC1CH1, - COMP_INMSEL_DAC1CH2, - COMP_INMSEL_PIN -}; - -/* Output selection */ - -enum stm32_comp_outsel_e -{ - COMP_OUTSEL_NOSEL, -#if defined(CONFIG_STM32_STM32F33XX) - COMP_OUTSEL_BRKACTH, - COMP_OUTSEL_BRK2, - COMP_OUTSEL_T1OCC, /* COMP2 only */ - COMP_OUTSEL_T3CAP3, /* COMP4 only */ - COMP_OUTSEL_T2CAP2, /* COMP6 only */ - COMP_OUTSEL_T1CAP1, /* COMP2 only */ - COMP_OUTSEL_T2CAP4, /* COMP2 only */ - COMP_OUTSEL_T15CAP2, /* COMP4 only */ - COMP_OUTSEL_T2OCC, /* COMP6 only */ - COMP_OUTSEL_T16OCC, /* COMP2 only */ - COMP_OUTSEL_T3CAP1, /* COMP2 only */ - COMP_OUTSEL_T15OCC, /* COMP4 only */ - COMP_OUTSEL_T16CAP1, /* COMP6 only */ - COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ -#endif -}; - -/* CSR register lock state */ - -enum stm32_comp_lock_e -{ - COMP_LOCK_RW, - COMP_LOCK_RO -}; - -#ifndef CONFIG_STM32_STM32F33XX - -/* Hysteresis */ - -enum stm32_comp_hyst_e -{ - COMP_HYST_DIS, - COMP_HYST_LOW, - COMP_HYST_MEDIUM, - COMP_HYST_HIGH -}; - -/* Power/Speed Modes */ - -enum stm32_comp_mode_e -{ - COMP_MODE_HIGHSPEED, - COMP_MODE_MEDIUMSPEED, - COMP_MODE_LOWPOWER, - COMP_MODE_ULTRALOWPOWER -}; - -/* Window mode */ - -enum stm32_comp_winmode_e -{ - COMP_WINMODE_DIS, - COMP_WINMODE_EN -}; - -#endif - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -192,5 +84,4 @@ FAR struct comp_dev_s *stm32_compinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM23_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32/stm32_comp_v1.c b/arch/arm/src/stm32/stm32_comp_v1.c index c8b658f..988c1f6 100644 --- a/arch/arm/src/stm32/stm32_comp_v1.c +++ b/arch/arm/src/stm32/stm32_comp_v1.c @@ -22,20 +22,9 @@ * Included Files ****************************************************************************/ -#include <nuttx/config.h> - -#include <stdint.h> -#include <errno.h> -#include <assert.h> -#include <debug.h> - -#include <arch/board/board.h> -#include <nuttx/analog/comp.h> -#include <nuttx/analog/ioctl.h> - -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_comp.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ /* Some COMP peripheral must be enabled */ @@ -68,10 +57,6 @@ # endif #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /* COMP2 default configuration **********************************************/ #ifdef CONFIG_STM32_COMP2 diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp_v1.h similarity index 76% copy from arch/arm/src/stm32/stm32_comp.h copy to arch/arm/src/stm32/stm32_comp_v1.h index 1212911..1239f97 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/stm32/stm32_comp_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp.h + * arch/arm/src/stm32/stm32_comp_v1.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,19 +18,13 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H +#define __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H /**************************************************************************** * Included Files ****************************************************************************/ -#include <nuttx/config.h> - -#include "chip.h" - -#include "hardware/stm32_comp.h" - #ifdef CONFIG_STM32_COMP /**************************************************************************** @@ -153,44 +147,5 @@ enum stm32_comp_winmode_e #endif -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_compinitialize - * - * Description: - * Initialize the COMP. - * - * Input Parameters: - * intf - The COMP interface number. - * - * Returned Value: - * Valid COMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the COMP block has enabled, - * 2. Board-specific logic has already configured - * - ****************************************************************************/ - -FAR struct comp_dev_s *stm32_compinitialize(int intf); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - #endif /* CONFIG_STM23_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.c b/arch/arm/src/stm32/stm32_comp_v2.c similarity index 53% copy from arch/arm/src/stm32/stm32_comp_v1.c copy to arch/arm/src/stm32/stm32_comp_v2.c index c8b658f..47a47ee 100644 --- a/arch/arm/src/stm32/stm32_comp_v1.c +++ b/arch/arm/src/stm32/stm32_comp_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.c + * arch/arm/src/stm32/stm32_comp_v2.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -22,126 +22,37 @@ * Included Files ****************************************************************************/ -#include <nuttx/config.h> - -#include <stdint.h> -#include <errno.h> -#include <assert.h> -#include <debug.h> - -#include <arch/board/board.h> -#include <nuttx/analog/comp.h> -#include <nuttx/analog/ioctl.h> - -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_comp.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ -/* Some COMP peripheral must be enabled */ +/* Some COMP peripheral must be enabled and the device must be supported */ -/* Up to 7 comparators in STM32F3 Series */ +#define DEVICE_NOT_SUPPORTED -#if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) || defined(CONFIG_STM32_COMP4) || \ - defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ - defined(CONFIG_STM32_COMP7) +#if defined(CONFIG_STM32_COMP) #ifndef CONFIG_STM32_SYSCFG # error "SYSCFG clock enable must be set" #endif -/* @TODO: support for STM32F30XX and STM32F37XX comparators */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) - -/* Currently only STM32F33XX supported */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) -# error "Not supported yet" -#endif - -#if defined(CONFIG_STM32_STM32F33XX) -# if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP7) -# error "STM32F33 supports only COMP2, COMP4 and COMP6" +#if defined(CONFIG_STM32_STM32G43XX) +# undef DEVICE_NOT_SUPPORTED +# if defined(CONFIG_STM32_COMP5) || defined(CONFIG_STM32_COMP6) || \ + defined(CONFIG_STM32_COMP7) +# error "STM32G43XX supports only COMP1, COMP2, COMP3 and COMP4" # endif #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* COMP2 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP2 -# ifndef COMP2_BLANLKING -# define COMP2_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP2_POL -# define COMP2_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP2_INM -# define COMP2_INM COMP_INM_DEFAULT -# endif -# ifndef COMP2_OUTSEL -# define COMP2_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP2_LOCK -# define COMP2_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP2_INM -# warning "GPIO_COMP2_INM not selected. Set default value to GPIO_COMP2_INM1" -# define GPIO_COMP2_INM GPIO_COMP2_INM_1 -# endif +#if defined(DEVICE_NOT_SUPPORTED) +# error "Device not supported" #endif -/* COMP4 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP4 -# ifndef COMP4_BLANLKING -# define COMP4_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP4_POL -# define COMP4_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP4_INM -# define COMP4_INM COMP_INM_DEFAULT -# endif -# ifndef COMP4_OUTSEL -# define COMP4_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP4_LOCK -# define COMP4_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP4_INM -# warning "GPIO_COMP4_INM not selected. Set default value to GPIO_COMP4_INM1" -# define GPIO_COMP4_INM GPIO_COMP4_INM_1 -# endif -#endif - -/* COMP6 default configuration **********************************************/ - -#ifdef CONFIG_STM32_COMP6 -# ifndef COMP6_BLANLKING -# define COMP6_BLANKING COMP_BLANKING_DEFAULT -# endif -# ifndef COMP6_POL -# define COMP6_POL COMP_BLANKING_DEFAULT -# endif -# ifndef COMP6_INM -# define COMP6_INM COMP_INM_DEFAULT -# endif -# ifndef COMP6_OUTSEL -# define COMP6_OUTSEL COMP_OUTSEL_DEFAULT -# endif -# ifndef COMP6_LOCK -# define COMP6_LOCK COMP_LOCK_DEFAULT -# endif -# ifndef GPIO_COMP6_INM -# warning "GPIO_COMP6_INM not selected. Set default value to GPIO_COMP6_INM1" -# define GPIO_COMP6_INM GPIO_COMP6_INM_1 -# endif +#if defined(CONFIG_STM32_COMP1_OUT) || defined(CONFIG_STM32_COMP2_OUT) || \ + defined(CONFIG_STM32_COMP3_OUT) || defined(CONFIG_STM32_COMP4_OUT) || \ + defined(CONFIG_STM32_COMP5_OUT) || defined(CONFIG_STM32_COMP6_OUT) || \ + defined(CONFIG_STM32_COMP7_OUT) +# define COMP_OUT_GPIO #endif /**************************************************************************** @@ -152,17 +63,15 @@ struct stm32_comp_s { - uint8_t blanking; /* Blanking source */ - uint8_t pol; /* Output polarity */ uint8_t inm; /* Inverting input selection */ - uint8_t out; /* Comparator output */ + uint32_t gpio_inm; /* Inverting input pin */ + uint8_t inp; /* Non inverting input selection */ + uint32_t gpio_inp; /* Non-inverting input pin */ + uint8_t pol; /* Output polarity */ + uint8_t hyst; /* Comparator hysteresis */ + uint8_t blanking; /* Blanking source */ uint8_t lock; /* Comparator Lock */ uint32_t csr; /* Control and status register */ -#ifndef CONFIG_STM32_STM32F33XX - uint8_t mode; /* Comparator mode */ - uint8_t hyst; /* Comparator hysteresis */ - /* @TODO: Window mode + INP selection */ -#endif }; /**************************************************************************** @@ -171,31 +80,38 @@ struct stm32_comp_s /* COMP Register access */ -static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, +static inline void comp_modify_csr(FAR struct stm32_comp_s *priv, uint32_t clearbits, uint32_t setbits); static inline uint32_t comp_getreg_csr(FAR struct stm32_comp_s *priv); -static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, +static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, uint32_t value); -static bool stm32_complock_get(FAR struct stm32_comp_s *priv); -static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock); /* COMP Driver Methods */ +#if defined (CONFIG_COMP) static void comp_shutdown(FAR struct comp_dev_s *dev); -static int comp_setup(FAR struct comp_dev_s *dev); -static int comp_read(FAR struct comp_dev_s *dev); -static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, +static int comp_setup(FAR struct comp_dev_s *dev); +static int comp_read(FAR struct comp_dev_s *dev); +static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, unsigned long arg); +#endif -/* Initialization */ +static int comp_config(FAR struct stm32_comp_s *priv); +static int comp_enable(FAR struct stm32_comp_s *priv, bool enable); +static bool comp_lock_get(FAR struct stm32_comp_s *priv); +static int comp_lock_set(FAR struct stm32_comp_s *priv, bool lock); -static int stm32_compconfig(FAR struct stm32_comp_s *priv); -static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable); +static int comp_config_inmpin(FAR struct stm32_comp_s *priv); +static int comp_config_inppin(FAR struct stm32_comp_s *priv); +#if defined(COMP_OUT_GPIO) +static int comp_config_outpin(FAR struct stm32_comp_s *priv); +#endif /**************************************************************************** * Private Data ****************************************************************************/ +#ifdef CONFIG_COMP static const struct comp_ops_s g_compops = { .ao_shutdown = comp_shutdown, @@ -203,25 +119,26 @@ static const struct comp_ops_s g_compops = .ao_read = comp_read, .ao_ioctl = comp_ioctl, }; +#endif #ifdef CONFIG_STM32_COMP1 static struct stm32_comp_s g_comp1priv = { - .blanking = COMP1_BLANKING, - .pol = COMP1_POL, - .inm = COMP1_INM, - .out = COMP1_OUTSEL, - .lock = COMP1_LOCK, - .csr = STM32_COMP1_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP1_MODE, - .hyst = COMP1_HYST, -#endif + .inm = CONFIG_STM32_COMP1_INM, + .inp = CONFIG_STM32_COMP1_INP, + .pol = CONFIG_STM32_COMP1_POL, + .hyst = CONFIG_STM32_COMP1_HYST, + .blanking = CONFIG_STM32_COMP1_BLANKSEL, + .lock = CONFIG_STM32_COMP1_LOCK, + .gpio_inp = GPIO_COMP1_INP, + .csr = STM32_COMP1_CSR }; static struct comp_dev_s g_comp1dev = { +#ifdef CONFIG_COMP .ad_ops = &g_compops, +#endif .ad_priv = &g_comp1priv, }; #endif @@ -229,21 +146,21 @@ static struct comp_dev_s g_comp1dev = #ifdef CONFIG_STM32_COMP2 static struct stm32_comp_s g_comp2priv = { - .blanking = COMP2_BLANKING, - .pol = COMP2_POL, - .inm = COMP2_INM, - .out = COMP2_OUTSEL, - .lock = COMP2_LOCK, - .csr = STM32_COMP2_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP2_MODE, - .hyst = COMP2_HYST, -#endif + .inm = CONFIG_STM32_COMP2_INM, + .inp = CONFIG_STM32_COMP2_INP, + .pol = CONFIG_STM32_COMP2_POL, + .hyst = CONFIG_STM32_COMP2_HYST, + .blanking = CONFIG_STM32_COMP2_BLANKSEL, + .lock = CONFIG_STM32_COMP2_LOCK, + .gpio_inp = GPIO_COMP2_INP, + .csr = STM32_COMP2_CSR }; static struct comp_dev_s g_comp2dev = { +#ifdef CONFIG_COMP .ad_ops = &g_compops, +#endif .ad_priv = &g_comp2priv, }; #endif @@ -251,21 +168,21 @@ static struct comp_dev_s g_comp2dev = #ifdef CONFIG_STM32_COMP3 static struct stm32_comp_s g_comp3priv = { - .blanking = COMP3_BLANKING, - .pol = COMP3_POL, - .inm = COMP3_INM, - .out = COMP3_OUTSEL, - .lock = COMP3_LOCK, - .csr = STM32_COMP3_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP3_MODE, - .hyst = COMP3_HYST, -#endif + .inm = CONFIG_STM32_COMP3_INM, + .inp = CONFIG_STM32_COMP3_INP, + .pol = CONFIG_STM32_COMP3_POL, + .hyst = CONFIG_STM32_COMP3_HYST, + .blanking = CONFIG_STM32_COMP3_BLANKSEL, + .lock = CONFIG_STM32_COMP3_LOCK, + .gpio_inp = GPIO_COMP3_INP, + .csr = STM32_COMP3_CSR }; static struct comp_dev_s g_comp3dev = { +#ifdef CONFIG_COMP .ad_ops = &g_compops, +#endif .ad_priv = &g_comp3priv, }; #endif @@ -273,21 +190,21 @@ static struct comp_dev_s g_comp3dev = #ifdef CONFIG_STM32_COMP4 static struct stm32_comp_s g_comp4priv = { - .blanking = COMP4_BLANKING, - .pol = COMP4_POL, - .inm = COMP4_INM, - .out = COMP4_OUTSEL, - .lock = COMP4_LOCK, - .csr = STM32_COMP4_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP4_MODE, - .hyst = COMP4_HYST, -#endif + .inm = CONFIG_STM32_COMP4_INM, + .inp = CONFIG_STM32_COMP4_INP, + .pol = CONFIG_STM32_COMP4_POL, + .hyst = CONFIG_STM32_COMP4_HYST, + .blanking = CONFIG_STM32_COMP4_BLANKSEL, + .lock = CONFIG_STM32_COMP4_LOCK, + .gpio_inp = GPIO_COMP4_INP, + .csr = STM32_COMP4_CSR }; static struct comp_dev_s g_comp4dev = { +#ifdef CONFIG_COMP .ad_ops = &g_compops, +#endif .ad_priv = &g_comp4priv, }; #endif @@ -295,21 +212,21 @@ static struct comp_dev_s g_comp4dev = #ifdef CONFIG_STM32_COMP5 static struct stm32_comp_s g_comp5priv = { - .blanking = COMP5_BLANKING, - .pol = COMP5_POL, - .inm = COMP5_INM, - .out = COMP5_OUTSEL, - .lock = COMP5_LOCK, - .csr = STM32_COMP5_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP5_MODE, - .hyst = COMP5_HYST, -#endif + .inm = CONFIG_STM32_COMP5_INM, + .inp = CONFIG_STM32_COMP5_INP, + .pol = CONFIG_STM32_COMP5_POL, + .hyst = CONFIG_STM32_COMP5_HYST, + .blanking = CONFIG_STM32_COMP5_BLANKSEL, + .lock = CONFIG_STM32_COMP5_LOCK, + .gpio_inp = GPIO_COMP5_INP, + .csr = STM32_COMP5_CSR }; static struct comp_dev_s g_comp5dev = { +#ifdef CONFIG_COMP .ad_ops = &g_compops, +#endif .ad_priv = &g_comp5priv, }; #endif @@ -317,21 +234,21 @@ static struct comp_dev_s g_comp5dev = #ifdef CONFIG_STM32_COMP6 static struct stm32_comp_s g_comp6priv = { - .blanking = COMP6_BLANKING, - .pol = COMP6_POL, - .inm = COMP6_INM, - .out = COMP6_OUTSEL, - .lock = COMP6_LOCK, - .csr = STM32_COMP6_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP6_MODE, - .hyst = COMP6_HYST, -#endif + .inm = CONFIG_STM32_COMP6_INM, + .inp = CONFIG_STM32_COMP6_INP, + .pol = CONFIG_STM32_COMP6_POL, + .hyst = CONFIG_STM32_COMP6_HYST, + .blanking = CONFIG_STM32_COMP6_BLANKSEL, + .lock = CONFIG_STM32_COMP6_LOCK, + .gpio_inp = GPIO_COMP6_INP, + .csr = STM32_COMP6_CSR }; static struct comp_dev_s g_comp6dev = { +#ifdef CONFIG_COMP .ad_ops = &g_compops, +#endif .ad_priv = &g_comp6priv, }; #endif @@ -339,21 +256,21 @@ static struct comp_dev_s g_comp6dev = #ifdef CONFIG_STM32_COMP7 static struct stm32_comp_s g_comp7priv = { - .blanking = COMP7_BLANKING, - .pol = COMP7_POL, - .inm = COMP7_INM, - .out = COMP7_OUTSEL, - .lock = COMP7_LOCK, - .csr = STM32_COMP7_CSR, -#ifndef CONFIG_STM32_STM32F33XX - .mode = COMP7_MODE, - .hyst = COMP7_HYST, -#endif + .inm = CONFIG_STM32_COMP7_INM, + .inp = CONFIG_STM32_COMP7_INP, + .pol = CONFIG_STM32_COMP7_POL, + .hyst = CONFIG_STM32_COMP7_HYST, + .blanking = CONFIG_STM32_COMP7_BLANKSEL, + .lock = CONFIG_STM32_COMP7_LOCK, + .gpio_inp = GPIO_COMP7_INP, + .csr = STM32_COMP7_CSR }; static struct comp_dev_s g_comp7dev = { +#ifdef CONFIG_COMP .ad_ops = &g_compops, +#endif .ad_priv = &g_comp7priv, }; #endif @@ -431,7 +348,7 @@ static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, } /**************************************************************************** - * Name: stm32_comp_complock_get + * Name: comp_lock_get * * Description: * Get COMP lock bit state @@ -444,7 +361,7 @@ static inline void comp_putreg_csr(FAR struct stm32_comp_s *priv, * ****************************************************************************/ -static bool stm32_complock_get(FAR struct stm32_comp_s *priv) +static bool comp_lock_get(FAR struct stm32_comp_s *priv) { uint32_t regval; @@ -454,7 +371,7 @@ static bool stm32_complock_get(FAR struct stm32_comp_s *priv) } /**************************************************************************** - * Name: stm32_complock + * Name: comp_lock_set * * Description: * Lock comparator CSR register @@ -468,13 +385,9 @@ static bool stm32_complock_get(FAR struct stm32_comp_s *priv) * ****************************************************************************/ -static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock) +static int comp_lock_set(FAR struct stm32_comp_s *priv, bool lock) { - bool current; - - current = stm32_complock_get(priv); - - if (current) + if (comp_lock_get(priv)) { if (lock == false) { @@ -489,7 +402,7 @@ static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock) { comp_modify_csr(priv, 0, COMP_CSR_LOCK); - priv->lock = COMP_LOCK_RO; + priv->lock = 1; } } @@ -497,10 +410,12 @@ static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock) } /**************************************************************************** - * Name: stm32_compconfig + * Name: comp_config_inmpin * * Description: - * Configure comparator and used I/Os + * Configure comparator inverting input pin. The GPIO that COMPx inverting + * input will be assigned is dependent of comparator number and must be + * defined in board.h file. See table 196 in RM0440. * * Input Parameters: * priv - A reference to the COMP structure @@ -508,313 +423,323 @@ static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock) * Returned Value: * 0 on success, a negated errno value on failure * - * REVISIT: Where to config comparator output pin ? - * ****************************************************************************/ -static int stm32_compconfig(FAR struct stm32_comp_s *priv) +static int comp_config_inmpin(FAR struct stm32_comp_s *priv) { - uint32_t regval = 0; - int index; - - /* Get comparator index */ - - switch (priv->csr) +# if defined(CONFIG_STM32_COMP1) + if (priv->csr == STM32_COMP1_CSR) { -#ifdef CONFIG_STM32_COMP1 - case STM32_COMP1_CSR: - index = 1; - break; -#endif - -#ifdef CONFIG_STM32_COMP2 - case STM32_COMP2_CSR: - index = 2; - break; -#endif + stm32_configgpio(GPIO_COMP1_INM); + } +# endif -#ifdef CONFIG_STM32_COMP3 - case STM32_COMP3_CSR: - index = 3; - break; -#endif +# if defined(CONFIG_STM32_COMP2) + if (priv->csr == STM32_COMP2_CSR) + { + stm32_configgpio(GPIO_COMP2_INM); + } +# endif -#ifdef CONFIG_STM32_COMP4 - case STM32_COMP4_CSR: - index = 4; - break; -#endif +# if defined(CONFIG_STM32_COMP3) + if (priv->csr == STM32_COMP3_CSR) + { + stm32_configgpio(GPIO_COMP3_INM); + } +# endif -#ifdef CONFIG_STM32_COMP5 - case STM32_COMP5_CSR: - index = 5; - break; -#endif +# if defined(CONFIG_STM32_COMP4) + if (priv->csr == STM32_COMP4_CSR) + { + stm32_configgpio(GPIO_COMP4_INM); + } +# endif -#ifdef CONFIG_STM32_COMP6 - case STM32_COMP6_CSR: - index = 6; - break; -#endif +# if defined(CONFIG_STM32_COMP5) + if (priv->csr == STM32_COMP5_CSR) + { + stm32_configgpio(GPIO_COMP5_INM); + } +# endif -#ifdef CONFIG_STM32_COMP7 - case STM32_COMP7_CSR: - index = 7; - break; -#endif +# if defined(CONFIG_STM32_COMP6) + if (priv->csr == STM32_COMP6_CSR) + { + stm32_configgpio(GPIO_COMP6_INM); + } +# endif - default: - return -EINVAL; +# if defined(CONFIG_STM32_COMP7) + if (priv->csr == STM32_COMP7_CSR) + { + stm32_configgpio(GPIO_COMP7_INM); } +# endif - /* Configure non inverting input */ + return OK; +} - switch (index) +/**************************************************************************** + * Name: comp_config_inppin + * + * Description: + * Configure comparator non-inverting input pin. The IO pin that COMPx + * non-inverting input will be assigned is dependent of comparator number + * and must be defined in board.h file. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int comp_config_inppin(FAR struct stm32_comp_s *priv) +{ +# if defined(CONFIG_STM32_COMP1) + if (priv->csr == STM32_COMP1_CSR) { -#ifdef CONFIG_STM32_COMP1 - case 1: stm32_configgpio(GPIO_COMP1_INP); - break; -#endif + } +# endif -#ifdef CONFIG_STM32_COMP2 - case 2: +# if defined(CONFIG_STM32_COMP2) + if (priv->csr == STM32_COMP2_CSR) + { stm32_configgpio(GPIO_COMP2_INP); - break; -#endif + } +# endif -#ifdef CONFIG_STM32_COMP3 - case 3: +# if defined(CONFIG_STM32_COMP3) + if (priv->csr == STM32_COMP3_CSR) + { stm32_configgpio(GPIO_COMP3_INP); - break; -#endif + } +# endif -#ifdef CONFIG_STM32_COMP4 - case 4: +# if defined(CONFIG_STM32_COMP4) + if (priv->csr == STM32_COMP4_CSR) + { stm32_configgpio(GPIO_COMP4_INP); - break; -#endif + } +# endif -#ifdef CONFIG_STM32_COMP5 - case 5: +# if defined(CONFIG_STM32_COMP5) + if (priv->csr == STM32_COMP5_CSR) + { stm32_configgpio(GPIO_COMP5_INP); - break; -#endif + } +# endif -#ifdef CONFIG_STM32_COMP6 - case 6: +# if defined(CONFIG_STM32_COMP6) + if (priv->csr == STM32_COMP6_CSR) + { stm32_configgpio(GPIO_COMP6_INP); - break; -#endif - -#ifdef CONFIG_STM32_COMP7 - case 7: - stm32_configgpio(GPIO_COMP7_INP); - break; -#endif - - default: - return -EINVAL; } +# endif - /* Set Comparator inverting input */ - - switch (priv->inm) +# if defined(CONFIG_STM32_COMP7) + if (priv->csr == STM32_COMP7_CSR) { - case COMP_INMSEL_1P4VREF: - regval |= COMP_CSR_INMSEL_1P4VREF; - break; + stm32_configgpio(GPIO_COMP7_INP); + } +# endif - case COMP_INMSEL_1P2VREF: - regval |= COMP_CSR_INMSEL_1P2VREF; - break; + return OK; +} - case COMP_INMSEL_3P4VREF: - regval |= COMP_CSR_INMSEL_3P4VREF; - break; +/**************************************************************************** + * Name: comp_config_outpin + * + * Description: + * Configure comparator output GPIO pin. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ - case COMP_INMSEL_VREF: - regval |= COMP_CSR_INMSEL_VREF; - break; +#if defined(COMP_OUT_GPIO) +static int comp_config_outpin(FAR struct stm32_comp_s *priv) +{ +# if defined(CONFIG_STM32_COMP1_OUT) + if (priv->csr == STM32_COMP1_CSR) + { + stm32_configgpio(GPIO_COMP1_OUT); + } +# endif - case COMP_INMSEL_DAC1CH1: - regval |= COMP_CSR_INMSEL_DAC1CH1; - break; +# if defined(CONFIG_STM32_COMP2_OUT) + if (priv->csr == STM32_COMP2_CSR) + { + ainfo("\tOUT assigned to: GPIO\n"); + stm32_configgpio(GPIO_COMP2_OUT); + } +# endif - case COMP_INMSEL_DAC1CH2: - regval |= COMP_CSR_INMSEL_DAC1CH2; - break; +# if defined(CONFIG_STM32_COMP3_OUT) + if (priv->csr == STM32_COMP3_CSR) + { + stm32_configgpio(GPIO_COMP3_OUT); + } +# endif - case COMP_INMSEL_PIN: - { - /* INMSEL PIN configuration dependent on COMP index */ +# if defined(CONFIG_STM32_COMP4_OUT) + if (priv->csr == STM32_COMP4_CSR) + { + stm32_configgpio(GPIO_COMP4_OUT); + } +# endif - switch (index) - { - /* TODO: Inverting input pin configuration for COMP1/3/5/7 */ +# if defined(CONFIG_STM32_COMP5_OUT) + if (priv->csr == STM32_COMP5_CSR) + { + stm32_configgpio(GPIO_COMP5_OUT); + } +# endif -#ifdef CONFIG_STM32_COMP2 - case 2: - { - /* COMP2_INM can be PA2 or PA4 */ - - stm32_configgpio(GPIO_COMP2_INM); - regval |= (GPIO_COMP2_INM == GPIO_COMP2_INM_1 ? - COMP_CSR_INMSEL_PA2 : COMP_CSR_INMSEL_PA4); - break; - } -#endif +# if defined(CONFIG_STM32_COMP6_OUT) + if (priv->csr == STM32_COMP6_CSR) + { + stm32_configgpio(GPIO_COMP6_OUT); + } +# endif -#ifdef CONFIG_STM32_COMP4 - case 4: - { - /* COMP4_INM can be PB2 or PA4 */ - - stm32_configgpio(GPIO_COMP4_INM); - regval |= (GPIO_COMP4_INM == GPIO_COMP4_INM_1 ? - COMP_CSR_INMSEL_PB2 : COMP_CSR_INMSEL_PA4); - break; - } -#endif +# if defined(CONFIG_STM32_COMP7_OUT) + if (priv->csr == STM32_COMP7_CSR) + { + stm32_configgpio(GPIO_COMP7_OUT); + } +# endif -#ifdef CONFIG_STM32_COMP6 - case 6: - { - /* COMP6_INM can be PB15 or PA4 */ - - stm32_configgpio(GPIO_COMP6_INM); - regval |= (GPIO_COMP6_INM == GPIO_COMP6_INM_1 ? - COMP_CSR_INMSEL_PB15 : COMP_CSR_INMSEL_PA4); - break; - } -#endif + return OK; +} +#endif /* COMP_OUT_GPIO */ - default : - return -EINVAL; - } +/**************************************************************************** + * Name: comp_config + * + * Description: + * Configure comparator and used I/Os. The pin configuration and the input + * assignments are COMP index dependent. + * + * Input Parameters: + * priv - A reference to the COMP structure + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + * REVISIT: Where to config comparator output pin ? + * + ****************************************************************************/ - break; - } +static int comp_config(FAR struct stm32_comp_s *priv) +{ + uint32_t regval = 0; + uint32_t value = 0; - default: - return -EINVAL; - } + /* Configure COMPx inverting input. */ - /* Set Comparator output selection */ + value = priv->inm << COMP_CSR_INMSEL_SHIFT; - switch (priv->out) + switch (priv->inm) { - case COMP_OUTSEL_NOSEL: - regval |= COMP_CSR_OUTSEL_NOSEL; - break; + case COMP_INM_1_4_VREF: + case COMP_INM_1_2_VREF: + case COMP_INM_3_4_VREF: - case COMP_OUTSEL_BRKACTH: - regval |= COMP_CSR_OUTSEL_BRKACTH; - break; + value |= COMP_CSR_BRGEN; /* scaler resistor bridge enable */ - case COMP_OUTSEL_BRK2: - regval |= COMP_CSR_OUTSEL_BRK2; - break; + case COMP_INM_VREF: - case COMP_OUTSEL_T1OCC: - regval |= COMP_CSR_OUTSEL_T1OCC; - break; - - case COMP_OUTSEL_T3CAP3: - regval |= COMP_CSR_OUTSEL_T3CAP3; - break; + value |= COMP_CSR_SCALEN; /* VREFINT scaler enable */ + break; - case COMP_OUTSEL_T2CAP2: - regval |= COMP_CSR_OUTSEL_T2CAP2; - break; + case COMP_INM_DAC_1: + case COMP_INM_DAC_2: - case COMP_OUTSEL_T1CAP1: - regval |= COMP_CSR_OUTSEL_T1CAP1; - break; + break; - case COMP_OUTSEL_T2CAP4: - regval |= COMP_CSR_OUTSEL_T2CAP4; - break; + case COMP_INM_PIN_1: + case COMP_INM_PIN_2: - case COMP_OUTSEL_T15CAP2: - regval |= COMP_CSR_OUTSEL_T15CAP2; - break; + comp_config_inmpin(priv); + break; - case COMP_OUTSEL_T2OCC: - if (index == 2) - { - regval |= COMP2_CSR_OUTSEL_T2OCC; - } - else if (index == 6) - { - regval |= COMP6_CSR_OUTSEL_T2OCC; - } + default: + return -EINVAL; + } - break; + regval |= value; - case COMP_OUTSEL_T16OCC: - regval |= COMP_CSR_OUTSEL_T16OCC; - break; + /* Configure COMPx non-inverting input. */ - case COMP_OUTSEL_T3CAP1: - regval |= COMP_CSR_OUTSEL_T3CAP1; - break; + ainfo("\tINP assigned to GPIO%d\n", priv->inp); - case COMP_OUTSEL_T15OCC: - regval |= COMP_CSR_OUTSEL_T15OCC; - break; + value = priv->inp << COMP_CSR_INPSEL_SHIFT; + regval |= value; - case COMP_OUTSEL_T16CAP1: - regval |= COMP_CSR_OUTSEL_T16CAP1; - break; + comp_config_inppin(priv); - case COMP_OUTSEL_T3OCC: - regval |= COMP_CSR_OUTSEL_T3OCC; - break; + /* Configure COMPx polarity */ - default: - return -EINVAL; + if (priv->pol == COMP_POL_INVERTED) + { + value = COMP_CSR_POL; + regval |= value; } - /* Set Comparator output polarity */ - - regval |= (priv->pol == COMP_POL_INVERTED ? COMP_CSR_POL : 0); - - /* Set Comparator output blanking source */ + /* Configure COMPx hysteresis */ - switch (priv->blanking) + switch (priv->hyst) { - case COMP_BLANKING_DIS: - regval |= COMP_CSR_BLANKING_DIS; - break; - - case COMP_BLANKING_T1OC5: - regval |= COMP_CSR_BLANKING_T1OC5; - break; + case COMP_HYST_DIS: + case COMP_HYST_10MV: + case COMP_HYST_20MV: + case COMP_HYST_30MV: + case COMP_HYST_40MV: + case COMP_HYST_50MV: + case COMP_HYST_60MV: + case COMP_HYST_70MV: + + value = priv->hyst << COMP_CSR_HYST_SHIFT; + regval |= value; + break; - case COMP_BLANKING_T3OC4: - regval |= COMP_CSR_BLANKING_T3OC4; - break; + default: + return -EINVAL; + } - case COMP_BLANKING_T2OC3: - regval |= COMP_CSR_BLANKING_T2OC3; - break; + /* Configure COMPx blanking signal source */ - case COMP_BLANKING_T15OC1: - regval |= COMP_CSR_BLANKING_T15OC1; - break; + switch (priv->blanking) + { + case COMP_BLANKING_DIS: + case COMP_BLANKING_TIMX_OCY_1: + case COMP_BLANKING_TIMX_OCY_2: + case COMP_BLANKING_TIMX_OCY_3: + case COMP_BLANKING_TIMX_OCY_4: + case COMP_BLANKING_TIMX_OCY_5: + case COMP_BLANKING_TIMX_OCY_6: + case COMP_BLANKING_TIMX_OCY_7: + + value = priv->blanking << COMP_CSR_BLANKING_SHIFT; + regval |= value; + break; - case COMP_BLANKING_T2OC4: - regval |= COMP_CSR_BLANKING_T2OC4; - break; + default: + return -EINVAL; + } - case COMP_BLANKING_T15OC2: - regval |= COMP_CSR_BLANKING_T15OC1; - break; + /* Set Comparator output selection */ - default: - return -EINVAL; - } +#if defined(COMP_OUT_GPIO) + comp_config_outpin(priv); +#endif /* Save CSR register */ @@ -822,20 +747,20 @@ static int stm32_compconfig(FAR struct stm32_comp_s *priv) /* Enable Comparator */ - stm32_compenable(priv, true); + comp_enable(priv, true); /* Lock Comparator if needed */ - if (priv->lock == COMP_LOCK_RO) + if (priv->lock) { - stm32_complock(priv, true); + comp_lock_set(priv, true); } return OK; } /**************************************************************************** - * Name: stm32_compenable + * Name: comp_enable * * Description: * Enable/disable comparator @@ -849,13 +774,13 @@ static int stm32_compconfig(FAR struct stm32_comp_s *priv) * ****************************************************************************/ -static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable) +static int comp_enable(FAR struct stm32_comp_s *priv, bool enable) { bool lock; ainfo("enable: %d\n", enable ? 1 : 0); - lock = stm32_complock_get(priv); + lock = comp_lock_get(priv); if (lock) { @@ -883,12 +808,12 @@ static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable) } /**************************************************************************** - * Name: adc_setup + * Name: comp_setup * * Description: * Configure the COMP. This method is called the first time that the COMP - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching COMP interrupts. + * device is opened. This will occur when the port is first opened. This + * setup includes configuring and attaching COMP interrupts. * Interrupts are all disabled upon return. * * Input Parameters: @@ -897,18 +822,20 @@ static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable) * ****************************************************************************/ +#ifdef CONFIG_COMP static int comp_setup(FAR struct comp_dev_s *dev) { #warning "Missing logic" return OK; } +#endif /**************************************************************************** * Name: comp_shutdown * * Description: - * Disable the COMP. This method is called when the COMP device is closed. + * Disable the COMP. This method is called when the COMP device is closed. * This method reverses the operation the setup method. * Works only if COMP device is not locked. * @@ -919,10 +846,12 @@ static int comp_setup(FAR struct comp_dev_s *dev) * ****************************************************************************/ +#ifdef CONFIG_COMP static void comp_shutdown(FAR struct comp_dev_s *dev) { -#warning "Missing logic" +# warning "Missing logic" } +#endif /**************************************************************************** * Name: comp_read @@ -938,6 +867,7 @@ static void comp_shutdown(FAR struct comp_dev_s *dev) * ****************************************************************************/ +#ifdef CONFIG_COMP static int comp_read(FAR struct comp_dev_s *dev) { FAR struct stm32_comp_s *priv; @@ -946,8 +876,9 @@ static int comp_read(FAR struct comp_dev_s *dev) priv = dev->ad_priv; regval = comp_getreg_csr(priv); - return (((regval & COMP_CSR_OUT) == 0) ? 0 : 1); + return (((regval & COMP_CSR_VALUE) == 0) ? 0 : 1); } +#endif /**************************************************************************** * Name: comp_ioctl @@ -965,11 +896,13 @@ static int comp_read(FAR struct comp_dev_s *dev) * ****************************************************************************/ +#ifdef CONFIG_COMP static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, unsigned long arg) { #warning "Missing logic" return -ENOTTY; } +#endif /**************************************************************************** * Public Functions @@ -1059,7 +992,7 @@ FAR struct comp_dev_s *stm32_compinitialize(int intf) comp = dev->ad_priv; - ret = stm32_compconfig(comp); + ret = comp_config(comp); if (ret < 0) { aerr("ERROR: Failed to initialize COMP%d: %d\n", intf, ret); @@ -1069,10 +1002,4 @@ FAR struct comp_dev_s *stm32_compinitialize(int intf) return dev; } -#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX || - * CONFIG_STM32_STM32F37XX - */ - -#endif /* CONFIG_STM32_COMP2 || CONFIG_STM32_COMP4 || - * CONFIG_STM32_COMP6 - */ +#endif /* CONFIG_STM32_COMP */ diff --git a/arch/arm/src/stm32/stm32_comp_v2.h b/arch/arm/src/stm32/stm32_comp_v2.h new file mode 100644 index 0000000..7ad1e74 --- /dev/null +++ b/arch/arm/src/stm32/stm32_comp_v2.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_comp_v2.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H +#define __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifdef CONFIG_STM32_COMP + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Inverting input. See Table 196 in RM0440 */ + +enum stm32_comp_inm_e +{ + COMP_INM_1_4_VREF, + COMP_INM_1_2_VREF, + COMP_INM_3_4_VREF, + COMP_INM_VREF, + COMP_INM_DAC_1, + COMP_INM_DAC_2, + COMP_INM_PIN_1, + COMP_INM_PIN_2, +}; + +/* Non-inverting input. See Table 195 in RM0440 */ + +enum stm32_comp_inp_e +{ + COMP_INP_PIN_1, + COMP_INP_PIN_2, +}; + +/* Output polarity */ + +enum stm32_comp_pol_e +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; + +/* Hysteresis */ + +enum stm32_comp_hyst_e +{ + COMP_HYST_DIS, + COMP_HYST_10MV, + COMP_HYST_20MV, + COMP_HYST_30MV, + COMP_HYST_40MV, + COMP_HYST_50MV, + COMP_HYST_60MV, + COMP_HYST_70MV, +}; + +/* Blanking source */ + +enum stm32_comp_blanking_e +{ + COMP_BLANKING_DIS, + COMP_BLANKING_TIMX_OCY_1, + COMP_BLANKING_TIMX_OCY_2, + COMP_BLANKING_TIMX_OCY_3, + COMP_BLANKING_TIMX_OCY_4, + COMP_BLANKING_TIMX_OCY_5, + COMP_BLANKING_TIMX_OCY_6, + COMP_BLANKING_TIMX_OCY_7, +}; + +#endif /* CONFIG_STM32_COMP */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H */
