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commit f617c27a8c5819a5c82fc63b4b958de42803759c Author: Nathan Hartman <[email protected]> AuthorDate: Fri Jul 23 16:29:36 2021 -0400 arch: arm: stm32, stm32f0l0g0, stm32h7, stm32l4, stm32l5: Fix typos. arch/arm/src/stm32/stm32_foc.c, arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h, arch/arm/src/stm32h7/stm32_allocateheap.c, arch/arm/src/stm32h7/stm32_fmc.c, arch/arm/src/stm32h7/stm32_pmstandby.c, arch/arm/src/stm32h7/stm32_spi.h, arch/arm/src/stm32h7/stm32_spi_slave.c, arch/arm/src/stm32h7/stm32_wwdg.c, arch/arm/src/stm32l4/stm32l4_adc.h, arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h, arch/arm/src/stm32l5/stm32l5_gpio.c, arch/arm/src/stm32l5/stm32l5_gpio.h, arch/arm/src/stm32l5/stm32l5_irq.c, arch/arm/src/stm32l5/stm32l5_rcc.c, arch/arm/src/stm32l5/stm32l5_rcc.h, arch/arm/src/stm32l5/stm32l5_serial.c, and arch/arm/src/stm32l5/stm32l5_spi.c: * Fix typos in comments. No functional changes. --- arch/arm/src/stm32/stm32_foc.c | 2 +- arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h | 2 +- arch/arm/src/stm32h7/stm32_allocateheap.c | 2 +- arch/arm/src/stm32h7/stm32_fmc.c | 2 +- arch/arm/src/stm32h7/stm32_pmstandby.c | 2 +- arch/arm/src/stm32h7/stm32_spi.h | 2 +- arch/arm/src/stm32h7/stm32_spi_slave.c | 8 ++++---- arch/arm/src/stm32h7/stm32_wwdg.c | 8 ++++---- arch/arm/src/stm32l4/stm32l4_adc.h | 2 +- arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h | 4 ++-- arch/arm/src/stm32l5/stm32l5_gpio.c | 4 ++-- arch/arm/src/stm32l5/stm32l5_gpio.h | 2 +- arch/arm/src/stm32l5/stm32l5_irq.c | 4 ++-- arch/arm/src/stm32l5/stm32l5_rcc.c | 4 ++-- arch/arm/src/stm32l5/stm32l5_rcc.h | 6 +++--- arch/arm/src/stm32l5/stm32l5_serial.c | 6 +++--- arch/arm/src/stm32l5/stm32l5_spi.c | 2 +- 17 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/stm32/stm32_foc.c index 5a839c6..f13df66 100644 --- a/arch/arm/src/stm32/stm32_foc.c +++ b/arch/arm/src/stm32/stm32_foc.c @@ -1653,7 +1653,7 @@ static int stm32_foc_adc_handler(int irq, FAR void *context, FAR void *arg) STM32_ADC_INT_ACK(adc, pending); - /* Call interrupt handler if registerd */ + /* Call interrupt handler if registered */ if (foc_dev->adc_isr != NULL) { diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h index c746dfa..5a6247f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h @@ -61,7 +61,7 @@ # undef HAVE_ADC_VLCD #endif -/* Supprot for Low frequency mode */ +/* Support for Low frequency mode */ #ifdef CONFIG_STM32F0L0G0_ENERGYLITE # define HAVE_ADC_LFM diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index f74d749..2519750 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -91,7 +91,7 @@ * - BOARD_SDRAM2_SIZE, if defined, declares the size of SDRAM * at address STM32_FMC_BANK6. +1 to CONFIG_MM_REGIONS. * - * - Additionaly, you may use the following options to add one more region + * - Additionally, you may use the following options to add one more region * of memory to system heap: * * - CONFIG_ARCH_HAVE_HEAP2=y diff --git a/arch/arm/src/stm32h7/stm32_fmc.c b/arch/arm/src/stm32h7/stm32_fmc.c index 19bcf2d..934d867 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.c +++ b/arch/arm/src/stm32h7/stm32_fmc.c @@ -91,7 +91,7 @@ * BOARD_FMC_SDCR[1..2] - Initial value for SDRAM control registers for SDRAM * bank 1-2. Note that some bits in SDCR1 influence both SDRAM banks and * are unused in SDCR2! - * BOARD_FMC_SDTR[1..2] - Initial value for SDRAM timing registeres for SDRAM + * BOARD_FMC_SDTR[1..2] - Initial value for SDRAM timing registers for SDRAM * bank 1-2. Note that some bits in SDTR1 influence both SDRAM banks and * are unused in SDTR2! * BOARD_FMC_SDRAM_REFR_PERIOD - The SDRAM refresh rate period in FMC clocks, diff --git a/arch/arm/src/stm32h7/stm32_pmstandby.c b/arch/arm/src/stm32h7/stm32_pmstandby.c index 350efee..ed9eac7 100644 --- a/arch/arm/src/stm32h7/stm32_pmstandby.c +++ b/arch/arm/src/stm32h7/stm32_pmstandby.c @@ -69,7 +69,7 @@ void stm32_pmstandby(void) { uint32_t regval; - /* Clear the wake-up flags before reseting. */ + /* Clear the wake-up flags before resetting. */ modifyreg32(STM32_PWR_CPUCR, 0, STM32_PWR_CPUCR_CSSF); modifyreg32(STM32_PWR_WKUPCR, 0, STM32_PWR_WKUPC1 | STM32_PWR_WKUPC2 | diff --git a/arch/arm/src/stm32h7/stm32_spi.h b/arch/arm/src/stm32h7/stm32_spi.h index 45babad..9865d2a 100644 --- a/arch/arm/src/stm32h7/stm32_spi.h +++ b/arch/arm/src/stm32h7/stm32_spi.h @@ -75,7 +75,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus); * bus number * * Returned Value: - * Valid SPI device structure reference on succcess; a NULL on failure + * Valid SPI device structure reference on success; a NULL on failure * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c b/arch/arm/src/stm32h7/stm32_spi_slave.c index 193153c..1315b9f 100644 --- a/arch/arm/src/stm32h7/stm32_spi_slave.c +++ b/arch/arm/src/stm32h7/stm32_spi_slave.c @@ -1620,7 +1620,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) * Mode 0: CFG2.CPHA=0 and CFG2.CPOL=0 * Master: CFG2.MSTR=1 * 8-bit: CFG1.DSIZE=7 - * MSB tranmitted first: CFG2.LSBFRST=0 + * MSB transmitted first: CFG2.LSBFRST=0 * Replace NSS with SSI & SSI=1: CR1.SSI=1 CFG2.SSM=1 (prevent MODF err) * Two lines full duplex: CFG2.COMM=0 */ @@ -1673,7 +1673,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) nxsem_init(&priv->exclsem, 0, 1); #ifdef CONFIG_STM32H7_SPI_DMA - /* DMA will be started in the interrupt handler, syncronized to the master + /* DMA will be started in the interrupt handler, synchronized to the master * nss */ @@ -1722,10 +1722,10 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) * Initialize the selected SPI port(bus) to operate as spi slave * * Input Parameters: - * Port number (for hardware that has mutiple SPI interfaces) + * Port number (for hardware that has multiple SPI interfaces) * * Returned Value: - * Valid SPI device structure reference on succcess; a NULL on failure + * Valid SPI device structure reference on success; a NULL on failure * ****************************************************************************/ diff --git a/arch/arm/src/stm32h7/stm32_wwdg.c b/arch/arm/src/stm32h7/stm32_wwdg.c index 28c84cb..ea7155f 100644 --- a/arch/arm/src/stm32h7/stm32_wwdg.c +++ b/arch/arm/src/stm32h7/stm32_wwdg.c @@ -108,7 +108,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_setwindow(FAR struct stm32_lowerhalf_s *priv, uint8_t window); -/* Interrupt hanlding *******************************************************/ +/* Interrupt handling *******************************************************/ static int stm32_interrupt(int irq, FAR void *context, FAR void *arg); @@ -530,7 +530,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, * reload = timeout * Fwwdg / 1000 - 1 * * Where - * timeout is the desired timout in milliseconds + * timeout is the desired timeout in milliseconds * reload is the contents of T{5:0] * Fwwdg is the frequency of the WWDG clock */ @@ -543,7 +543,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, */ #if 0 - wdinfo("wdgtb=%d fwwdg=%d reload=%d timout=%d\n", + wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n", wdgtb, fwwdg, reload, 1000 * (reload + 1) / fwwdg); #endif if (reload <= WWDG_CR_T_MAX || wdgtb == 3) @@ -576,7 +576,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, priv->fwwdg = fwwdg; priv->reload = reload; - wdinfo("wdgtb=%d fwwdg=%d reload=%d timout=%d\n", + wdinfo("wdgtb=%d fwwdg=%d reload=%d timeout=%d\n", wdgtb, fwwdg, reload, priv->timeout); /* Set WDGTB[1:0] bits according to calculated value */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index 6002ad4..4c1edce 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -1132,7 +1132,7 @@ #ifdef CONFIG_STM32L4_ADC_LL_OPS -/* This structure provides the publicly visable representation of the +/* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h index be0dde3..d2dc00d 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h @@ -291,7 +291,7 @@ /* PLLSAI1 Configuration register */ -#define RCC_PLLSAI1CFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLSAI1 entry clock soure */ +#define RCC_PLLSAI1CFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLSAI1 entry clock source */ #define RCC_PLLSAI1CFG_PLLSRC_MASK (3 << RCC_PLLSAI1CFG_PLLSRC_SHIFT) # define RCC_PLLSAI1CFG_PLLSRC_NONE (0 << RCC_PLLSAI1CFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */ # define RCC_PLLSAI1CFG_PLLSRC_MSI (1 << RCC_PLLSAI1CFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */ @@ -339,7 +339,7 @@ /* PLLSAI2 Configuration register */ -#define RCC_PLLSAI2CFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLSAI2 entry clock soure */ +#define RCC_PLLSAI2CFG_PLLSRC_SHIFT (0) /* Bit 0-1: Main PLSAI2 entry clock source */ #define RCC_PLLSAI2CFG_PLLSRC_MASK (3 << RCC_PLLSAI2CFG_PLLSRC_SHIFT) # define RCC_PLLSAI2CFG_PLLSRC_NONE (0 << RCC_PLLSAI2CFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */ # define RCC_PLLSAI2CFG_PLLSRC_MSI (1 << RCC_PLLSAI2CFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */ diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index 44ea5db..1053f32 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -93,7 +93,7 @@ const uint32_t g_gpiobase[STM32L5_NPORTS] = * * Assumptions: * This function is called early in the initialization sequence so that - * no mutual exlusion is necessary. + * no mutual exclusion is necessary. * ****************************************************************************/ @@ -112,7 +112,7 @@ void stm32l5_gpioinit(void) * * Returned Value: * OK on success - * A negated errono valu on invalid port, or when pin is locked as ALT + * A negated errno value on invalid port, or when pin is locked as ALT * function. * * To-Do: Auto Power Enable diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index cce75ec..8b11fc6 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -155,7 +155,7 @@ /* If the pin is a GPIO digital output, then this identifies the initial * output value. If the pin is an input, this bit is overloaded to provide - * the qualifier to distinquish input pull-up and -down: + * the qualifier to distinguish input pull-up and -down: * * 1111 1111 1100 0000 0000 * 9876 5432 1098 7654 3210 diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index db1d6f6..b03f3eb 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -133,8 +133,8 @@ static void stm32l5_dumpnvic(const char *msg, int irq) * stm32l5_dbgmonitor, stm32l5_pendsv, stm32l5_reserved * * Description: - * Handlers for various execptions. None are handled and all are fatal - * error conditions. The only advantage these provided over the default + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provide over the default * unexpected interrupt handler is that they provide a diagnostic output. * ****************************************************************************/ diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index b18378d..5ab9ff7 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -198,9 +198,9 @@ void stm32l5_clockconfig(void) * operation * re-enable/re-start the PLL * - * This functional performs a subset of the operations performed by + * This function performs a subset of the operations performed by * stm32l5_clockconfig() - * reset the currenlty enabled peripheral clocks. + * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index fc3e815..b1ce5ac 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -131,7 +131,7 @@ void stm32l5_clockconfig(void); * * Description: * Any STM32L5 board may replace the "standard" board clock configuration - * logic with its own, custom clock cofiguration logic. + * logic with its own, custom clock configuration logic. * ****************************************************************************/ @@ -163,9 +163,9 @@ void stm32l5_stdclockconfig(void); * operation: When re-awakening from deep-sleep modes, it is necessary to * re-enable/re-start the PLL * - * This functional performs a subset of the operations performed by + * This function performs a subset of the operations performed by * stm32l5_clockconfig(): It does not reset any devices, and it does not - * reset the currenlty enabled peripheral clocks. + * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index b994415..2e3bf9b 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -1795,9 +1795,9 @@ static int stm32l5serial_interrupt(int irq, FAR void *context, FAR void *arg) * " " USART_ISR_ORE Overrun Error Detected * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) * - * NOTE: Some of these status bits must be cleared by explicity writing - * one to the ICR register: USART_ICR_CTSCF, USART_ICR_LBDCF. Note of - * those are currently being used. + * NOTE: Some of these status bits must be cleared by explicitly + * writing one to the ICR register: USART_ICR_CTSCF, USART_ICR_LBDCF. + * Note of those are currently being used. */ #ifdef HAVE_RS485 diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index b679c15..e209e42 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -1727,7 +1727,7 @@ static void spi_bus_initialize(FAR struct stm32l5_spidev_s *priv) * Mode 0: CR1.CPHA=0 and CR1.CPOL=0 * Master: CR1.MSTR=1 * 8-bit: CR2.DS=7 - * MSB tranmitted first: CR1.LSBFIRST=0 + * MSB transmitted first: CR1.LSBFIRST=0 * Replace NSS with SSI & SSI=1: CR1.SSI=1 CR1.SSM=1 * (prevents MODF error) * Two lines full duplex: CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care)
