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commit 21f59c874fa760ead68cf381bdc8dfd0bdb6bf75 Author: raiden00pl <[email protected]> AuthorDate: Mon Aug 9 21:34:39 2021 +0200 stm32/qenco: fix compilation for STM32F1. GTIM_CCER_CCxNP bits are not present in F1 --- arch/arm/src/stm32/stm32_qencoder.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index e3f99fc..18112cf 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -824,7 +824,11 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) /* Select the Polarity=rising and set the CC1E Bit */ +#ifdef HAVE_GTIM_CCXNP ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); +#else + ccer &= ~(GTIM_CCER_CC1P); +#endif ccer |= GTIM_CCER_CC1E; /* Write to TIM CCMR1 and CCER registers */ @@ -860,7 +864,11 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) /* Select the Polarity=rising and set the CC2E Bit */ +#ifdef HAVE_GTIM_CCXNP ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); +#else + ccer &= ~(GTIM_CCER_CC2P); +#endif ccer |= GTIM_CCER_CC2E; /* Write to TIM CCMR1 and CCER registers */
