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commit 7b43d114357d772ed3259de35e134fe30dc75586 Author: Abdelatif Guettouche <[email protected]> AuthorDate: Wed Oct 13 12:44:53 2021 +0200 esp32_spiflash.c: Allocate only one variable to hold the cache state in single CPU mode. Signed-off-by: Abdelatif Guettouche <[email protected]> --- arch/xtensa/src/esp32/esp32_spiflash.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c index 5060473..7c085ab 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.c +++ b/arch/xtensa/src/esp32/esp32_spiflash.c @@ -59,6 +59,12 @@ * Pre-processor Definitions ****************************************************************************/ +/* Used in spiflash_cachestate_s structure even when SMP is disabled. */ + +#ifndef CONFIG_SMP_NCPUS +# define CONFIG_SMP_NCPUS 1 +#endif + #define SPI_FLASH_WRITE_BUF_SIZE (32) #define SPI_FLASH_READ_BUF_SIZE (64) @@ -165,7 +171,7 @@ struct spiflash_cachestate_s int other; #endif irqstate_t flags; - uint32_t val[2]; + uint32_t val[CONFIG_SMP_NCPUS]; }; /****************************************************************************
