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commit 50222443396f6dbc53d36cb89e283033ff2c3e15 Author: David Sidrane <[email protected]> AuthorDate: Wed Oct 27 13:04:35 2021 -0700 imxrt mpuinit:Set Data and Code Type to Normal Strongly-Ordered requires aligned access unless caching is enabled. Normal memory Accesses to normal memory region are idempotent... - unaligned accesses can be supported --- arch/arm/src/imxrt/imxrt_mpuinit.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c index 061c3b0..394f9b6 100644 --- a/arch/arm/src/imxrt/imxrt_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -143,49 +143,49 @@ void imxrt_mpu_initialize(void) * Instruction access */ mpu_configure_region(IMXRT_FLEXCIPHER_BASE, 8 * 1024 * 1024, - MPU_RASR_TEX_SO | /* Ordered */ - MPU_RASR_C | /* Cacheable */ + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ MPU_RASR_B | /* Bufferable * Not Shareable */ MPU_RASR_AP_RORO); /* P:RO U:RO * Instruction access */ mpu_configure_region(IMXRT_ITCM_BASE, 128 * 1024, - MPU_RASR_TEX_SO | /* Ordered */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable * Not Shareable */ MPU_RASR_AP_RWRW); /* P:RW U:RW * Instruction access */ mpu_configure_region(IMXRT_DTCM_BASE, 128 * 1024, - MPU_RASR_TEX_SO | /* Ordered */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable * Not Shareable */ MPU_RASR_AP_RWRW); /* P:RW U:RW * Instruction access */ mpu_configure_region(IMXRT_OCRAM2_BASE, 512 * 1024, - MPU_RASR_TEX_SO | /* Ordered */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable * Not Shareable */ MPU_RASR_AP_RWRW); /* P:RW U:RW * Instruction access */ mpu_configure_region(IMXRT_OCRAM_BASE, 512 * 1024, - MPU_RASR_TEX_SO | /* Ordered */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable * Not Shareable */ MPU_RASR_AP_RWRW); /* P:RW U:RW * Instruction access */ mpu_configure_region(IMXRT_EXTMEM_BASE, 32 * 1024 * 1024, MPU_RASR_TEX_SO | /* Ordered */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable * Not Shareable */ MPU_RASR_AP_RWRW); /* P:RW U:RW * Instruction access */
