zhuyanlinzyl commented on pull request #5261: URL: https://github.com/apache/incubator-nuttx/pull/5261#issuecomment-1017250336
Yes, As Xtensa is configurable cores, in hardware chip design, our chip let timer interrupt in level-2 and level-3 interrupt level In interrupt higher than level one, the `EXCM` bit will not set by hardware when interrupt happen. I think it's the reason why we encounter this problem, but you do not. In you product, the timer interrupt run in level-1 interrupt level. @Ouss4 -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
