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The following commit(s) were added to refs/heads/master by this push:
new e545c44 arch/arm/samv7/sam_progmem: insert DMB instruction into data
write loop
e545c44 is described below
commit e545c440f4a97185ded366479a64767f39b4fd7f
Author: Petro Karashchenko <[email protected]>
AuthorDate: Fri Feb 4 19:42:13 2022 +0200
arch/arm/samv7/sam_progmem: insert DMB instruction into data write loop
This change fix the regression that was introduced with
https://github.com/apache/incubator-nuttx/pull/4904
In case if D-Cache in configured in Write-Through mode there is
Cortex-M7 erata 1313001 that describes a situation when linefill
buffer or cache contains stale data. Even if progmem write loop
does not fully matches the description there is a possibility
to program stale data if there is no DMB instruction after each
write operation to progmem latch buffer.
Signed-off-by: Petro Karashchenko <[email protected]>
---
arch/arm/src/samv7/sam_progmem.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/src/samv7/sam_progmem.c b/arch/arm/src/samv7/sam_progmem.c
index ed17fc3..02600a6 100644
--- a/arch/arm/src/samv7/sam_progmem.c
+++ b/arch/arm/src/samv7/sam_progmem.c
@@ -582,6 +582,10 @@ ssize_t up_progmem_write(size_t address, const void
*buffer, size_t buflen)
for (i = 0; i < SAMV7_PAGE_WORDS; i++)
{
*dest++ = *src++;
+
+#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
+ ARM_DMB();
+#endif
}
/* Flush the data cache to memory */
