anchao opened a new pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734
## Summary
In SVC mode, the banked register will be inconsistent with the user mode
register:
```
arch/arm/src/armv7-a/arm_vectors.S
276 .globl arm_syscall
277 .globl arm_vectorsvc
278 .type arm_vectorsvc, %function
279
280 arm_vectorsvc:
...
286 sub sp, sp, #XCPTCONTEXT_SIZE **// < SVC mode SP**
...
308 stmia r0, {r13, r14}^ **// < USR mode SP/LR**
...
```
```
[ 2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[ 2.200000] [ 4] [ ALERT] R0: 00000004 80001229 00000001 80202018
00000000 00000000 00000000 802027d0
[ 2.200000] [ 4] [ ALERT] R8: 00000000 00000000 00000000 00000000
00000000 802027d0 1080f710 1080f710
[ 2.200000] [ 4] [ ALERT] CPSR: 00000073
[ 2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[ 2.200000] [ 4] [ ALERT] R0: 1 80202018 1 80202018 0 0 0 802027d0
[ 2.200000] [ 4] [ ALERT] R8: 0 0 0 0 0 802027d0 1080f710 80001229
[ 2.200000] [ 4] [ ALERT] CPSR: 00000070
```
SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE
```
[ 2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[ 2.200000] [ 4] [ ALERT] R0: 00000033 00000000 80202780 00000000
00000000 00000000 00000000 80202710
[ 2.200000] [ 4] [ ALERT] R8: 00000000 00000000 00000000 00000000
00000000 80202710 800039d5 800039b2
[ 2.200000] [ 4] [ ALERT] CPSR: 00000070
[ 2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[ 2.200000] [ 4] [ ALERT] R0: 2b 0 80202780 0 0 0 0 80202710
[ 2.200000] [ 4] [ ALERT] R8: 0 0 0 0 0 10843d80 800039d5 10801425
[ 2.200000] [ 4] [ ALERT] CPSR: 00000073
```
SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode
This commit change the default CPU mode to System and ensure the consistency
of SP/LR in USR/SYS mode during syscall.
Signed-off-by: chao.an <anc...@xiaomi.com>
## Impact
armv7-a/r: PSR_MODE_SVC -> PSR_MODE_SYS
## Testing
sabre-6quad/netknsh (/mnt/nfs/bin/getprime)
sabre-6quad/smp(ostest)
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