pkarashchenko commented on a change in pull request #3172: URL: https://github.com/apache/incubator-nuttx/pull/3172#discussion_r837483473
########## File path: boards/arm/stm32h7/portenta-h7/include/board.h ########## @@ -0,0 +1,368 @@ +/**************************************************************************** + * boards/arm/stm32h7/portenta-h7/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H7_PORTENTA_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32H7_PORTENTA_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#ifndef __ASSEMBLY__ +# include <stdint.h> +#endif + +/* Do not include STM32 H7 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The board provides the following clock sources: + * + * NOTE: The documentation and schematics claim that there is a 27MHz + * oscillator for HSE. However, after much headache, it was measured + * to actually be 25MHz. Looking at some mbed code validates that they + * are using 25MHz as the HSE clock. This was further confirmed with the + * Arduino staff. + * + * U18: 25MHz HSE MEMS Oscillator + * Y1: 32768Hz LSE crystal oscillator + * + * So we have these clock source available within the STM32 + * + * HSI: 64 MHz RC factory-trimmed + * LSI: 32 KHz RC + * HSE: 27 MHz oscillator + * LSE: 32.768 kHz + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY 25000000ul +#define STM32_LSE_FREQUENCY 32768 + +#define STM32_BOARD_USEHSE +#define STM32_HSEBYP_ENABLE + +/* Main PLL Configuration. + * + * PLL source is HSE = 25,000,000 + * + * When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected. + * VCOH otherwise. + * + * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * Subject to: + * + * 1 <= PLLM <= 63 + * 4 <= PLLN <= 512 + * 150 MHz <= PLL_VCOL <= 420MHz + * 192 MHz <= PLL_VCOH <= 836MHz + * + * SYSCLK = PLL_VCO / PLLP + * CPUCLK = SYSCLK / D1CPRE + * Subject to + * + * PLLP1 = {2, 4, 6, 8, ..., 128} + * PLLP2,3 = {2, 3, 4, ..., 128} + * CPUCLK <= 480 MHz + */ + +#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE + +/* PLL1, wide 2 - 4 MHz input, enable DIVP, DIVQ, DIVR + * + * PLL1_VCO = (25,000,000 / 5) * 160 = 800 MHz + * + * PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 400 MHz + * PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 200 MHz + * PLL1R = PLL1_VCO/8 = 960 MHz / 8 = 100 MHz + */ + +#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL1RGE_2_4_MHZ | \ + RCC_PLLCFGR_DIVP1EN | \ + RCC_PLLCFGR_DIVQ1EN | \ + RCC_PLLCFGR_DIVR1EN) +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(5) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(160) +#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) +#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) + +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 5) * 160) +#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) +#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) + +/* PLL2 */ + +#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL2RGE_2_4_MHZ | \ + RCC_PLLCFGR_DIVP2EN) +#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(5) +#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(160) +#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(2) +#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(4) +#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(8) + +#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 5) * 160) +#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2) +#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 4) +#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 8) + +/* PLL3 */ + +#define STM32_PLLCFG_PLL3CFG 0 +#define STM32_PLLCFG_PLL3M 0 +#define STM32_PLLCFG_PLL3N 0 +#define STM32_PLLCFG_PLL3P 0 +#define STM32_PLLCFG_PLL3Q 0 +#define STM32_PLLCFG_PLL3R 0 + +#define STM32_VCO3_FREQUENCY +#define STM32_PLL3P_FREQUENCY +#define STM32_PLL3Q_FREQUENCY +#define STM32_PLL3R_FREQUENCY Review comment: @microhobby could you please answer this? -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
