pkarashchenko commented on code in PR #6003:
URL: https://github.com/apache/incubator-nuttx/pull/6003#discussion_r844965873
##########
arch/risc-v/src/esp32c3/esp32c3_irq.c:
##########
@@ -371,38 +371,32 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t
mcause, uintptr_t *regs)
irqinfo("INFO: mcause=%08" PRIXPTR "\n", mcause);
- if ((RISCV_IRQ_BIT & mcause) != 0)
- {
- uint8_t cpuint = mcause & RISCV_IRQ_MASK;
-
- DEBUGASSERT(cpuint <= ESP32C3_CPUINT_MAX);
+ DEBUGASSERT(cpuint <= ESP32C3_CPUINT_MAX);
- irqinfo("INFO: cpuint=%" PRIu8 "\n", cpuint);
+ irqinfo("INFO: cpuint=%" PRIu8 "\n", cpuint);
+ if ((RISCV_IRQ_BIT & mcause) != 0)
+ {
/* Clear edge interrupts. */
putreg32(1 << cpuint, INTERRUPT_CPU_INT_CLEAR_REG);
-
irq = g_cpuint_map[cpuint] + ESP32C3_IRQ_FIRSTPERIPH;
- regs = riscv_doirq(irq, regs);
-
- /* Toggle the bit back to zero. */
-
- putreg32(0, INTERRUPT_CPU_INT_CLEAR_REG);
}
else
{
- if (mcause == RISCV_IRQ_ECALLM)
- {
- *mepc += 4;
- regs = riscv_doirq(ESP32C3_IRQ_ECALL_M, regs);
- }
- else
- {
- riscv_exception(mcause, regs);
- }
+ irq = mcause;
}
+ if (mcause == RISCV_IRQ_ECALLM)
+ regs[REG_EPC] += 4;
+
+ regs = riscv_doirq(irq, regs);
+
+ /* Toggle the bit back to zero. */
+
+ if ((RISCV_IRQ_BIT & mcause) != 0)
+ putreg32(0, INTERRUPT_CPU_INT_CLEAR_REG);
Review Comment:
```suggestion
if ((RISCV_IRQ_BIT & mcause) != 0)
{
putreg32(0, INTERRUPT_CPU_INT_CLEAR_REG);
}
```
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