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from 98d8d2a1ff arch/xtensa: Group all the macros in one file.
add d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem
mapped MTIMER currten value regs.
No new revisions were added by this update.
Summary of changes:
arch/risc-v/src/common/riscv_mtimer.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
