hartmannathan commented on code in PR #6478: URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r905001017
########## tools/ci/testlist/macos.dat: ########## @@ -36,3 +36,9 @@ # x86_64 /x86_64/intel64/qemu-intel64/configs/nsh + +# The gcc 11.2 toolcain for MACOS maybe fail when compile +# with float, disable the cibuild check for MACOS +# it will be enbale while new toolchain release Review Comment: s/enbale/enabled/ ########## arch/arm64/src/common/arm64_initialstate.c: ########## @@ -0,0 +1,154 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_initialstate.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> +#include <arch/limits.h> + +#include <nuttx/arch.h> +#include <nuttx/board.h> +#include <nuttx/drivers/drivers.h> +#include <nuttx/fs/loop.h> +#include <nuttx/net/loopback.h> +#include <nuttx/net/tun.h> +#include <nuttx/net/telnet.h> +#include <nuttx/note/note_driver.h> +#include <nuttx/syslog/syslog_console.h> +#include <nuttx/serial/pty.h> +#include <nuttx/crypto/crypto.h> +#include <nuttx/power/pm.h> +#include <arch/chip/chip.h> + +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "chip.h" +#include "arm64_fatal.h" + +#ifdef CONFIG_ARCH_FPU +#include "arm64_fpu.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void arm64_new_task(struct tcb_s * tcb) +{ + char * stack_ptr = tcb->stack_base_ptr + tcb->adj_stack_size; + struct regs_context * pinitctx; + +#ifdef CONFIG_ARCH_FPU + struct fpu_reg * pfpuctx; + pfpuctx = STACK_PTR_TO_FRAME(struct fpu_reg, stack_ptr); + tcb->xcp.fpu_regs = pfpuctx; + + /* set fpu context */ + + arm64_init_fpu(tcb); + stack_ptr = (char *)pfpuctx; +#endif + + pinitctx = STACK_PTR_TO_FRAME(struct regs_context, stack_ptr); + memset(pinitctx, 0, sizeof(struct regs_context)); + pinitctx->elr = (uint64_t)tcb->start; + + /* Keep using SP_EL1 */ + + pinitctx->spsr = SPSR_MODE_EL1H; + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + pinitctx->spsr |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT); +#endif /* CONFIG_SUPPRESS_INTERRUPTS */ + + pinitctx->sp_elx = (uint64_t)pinitctx; + pinitctx->sp_el0 = (uint64_t)pinitctx; + pinitctx->exe_depth = 0; + pinitctx->tpidr_el0 = (uint64_t)tcb; + pinitctx->tpidr_el1 = (uint64_t)tcb; + + tcb->xcp.regs = (uint64_t *)pinitctx; +} + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB has been created. This + * function is called to initialize the processor specific portions of + * the new TCB. + * + * This function must setup the initial architecture registers and/or + * stack so that execution will begin at tcb->start on the next context + * switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; + + memset(xcp, 0, sizeof(struct xcptcontext)); + + if (tcb->pid < CONFIG_SMP_NCPUS) + { + /* Initialize the idle thread stack */ +#ifdef CONFIG_SMP + tcb->stack_alloc_ptr = (void *)(g_cpu_idlestackalloc[0]); +#else + tcb->stack_alloc_ptr = (void *)(g_idle_stack); +#endif + tcb->stack_base_ptr = tcb->stack_alloc_ptr; + tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE; + +#ifdef CONFIG_ARCH_FPU + /* set fpu context */ + + arm64_init_fpu(tcb); +#endif + /* set initialize idle thread id and exeception depth */ Review Comment: s/exeception/exception/ ########## arch/arm64/src/common/arm64_head.S: ########## @@ -0,0 +1,291 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_head.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * DESCRIPTION + * Bring-up code for ARMv8. + * Based on head.S(arm64 porting) at Xen Hypervisor Project + * Based on reset.S(aarch64 porting) at Zephyr RTOS Project + * + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "arm64_arch.h" +#include "arm64_macro.inc" + +/* macro define from xen head, for efi head define */ +#define PAGE_SHIFT 12 +#define __HEAD_FLAG_PAGE_SIZE ((PAGE_SHIFT - 10) / 2) + +#define __HEAD_FLAG_PHYS_BASE 1 + + +#define __HEAD_FLAGS ((__HEAD_FLAG_PAGE_SIZE << 1) | \ + (__HEAD_FLAG_PHYS_BASE << 3)) + +#ifdef CONFIG_DEBUG_FEATURES + +#define RODATA_STR(label, msg) \ +.pushsection .rodata.str, "aMS", %progbits, 1 ; \ +label: .asciz msg; \ +.popsection + +/* Macro to print a string to the UART, if there is one. + * Clobbers x0 - x3, x30 is lr for return + */ +#define PRINT(_s) \ + mov x3, x30 ; \ + adr x1, 98f ; \ + bl boot_stage_puts; \ + mov x30, x3 ; \ + RODATA_STR(98, _s) +#else +#define PRINT(s) +#endif /* CONFIG_DEBUG_FEATURES */ + + /* Kernel startup entry point. + * --------------------------- + * + * The requirements are: + * MMU = off, D-cache = off, I-cache = on or off, + * x0 = physical address to the FDT blob. + * it will be used when NuttX support divice tree in the feature + * + * This must be the very first address in the loaded image. + * It should be loaded at any 4K-aligned address. + */ + .globl __start; +__start: + + /* DO NOT MODIFY. Image header expected by Linux boot-loaders. + * + * This add instruction has no meaningful effect except that + * its opcode forms the magic "MZ" signature of a PE/COFF file + * that is required for UEFI applications. + * + * Some bootloader (such imx8 uboot) checking the magic "MZ" to see + * if the image is a valid Linux image. but modifing the bootLoader is Review Comment: s/modifing/modifying/ ########## arch/arm64/src/common/arm64_syscall.c: ########## @@ -0,0 +1,541 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_syscall.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <inttypes.h> +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <debug.h> +#include <syscall.h> + +#include <nuttx/arch.h> +#include <nuttx/sched.h> +#include <nuttx/addrenv.h> + +#include "arch/irq.h" +#include "signal/signal.h" +#include "addrenv.h" +#include "arm64_internal.h" +#include "arm64_fatal.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: dispatch_syscall + * + * Description: + * Call the stub function corresponding to the system call. NOTE the non- + * standard parameter passing: + * + * x0 = SYS_ call number + * x1 = parm0 + * x2 = parm1 + * x3 = parm2 + * x4 = parm3 + * x5 = parm4 + * x6 = parm5 + * + * The values of X4-X5 may be preserved in the proxy called by the user + * code if they are used (but otherwise will not be). + * + * WARNING: There are hard-coded values in this logic! + * + ****************************************************************************/ + +#ifdef CONFIG_LIB_SYSCALL +static void dispatch_syscall(void) naked_function; +static void dispatch_syscall(void) +{ + __asm__ __volatile__ + ( + " sub sp, sp, #16\n" /* Create a stack frame to hold 3 parms + lr */ + " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */ + " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */ + " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */ + " str lr, [sp, #12]\n" /* Save lr in the stack frame */ + " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */ + " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */ + " blx ip\n" /* Call the stub (modifies lr) */ + " ldr lr, [sp, #12]\n" /* Restore lr */ + " add sp, sp, #16\n" /* Destroy the stack frame */ + " mov r2, r0\n" /* R2=Save return value in R2 */ + " mov r0, %0\n" /* R0=SYS_syscall_return */ + " svc %1\n"::"i"(SYS_syscall_return), + "i"(SYS_syscall) /* Return from the SYSCALL */ + ); +} +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void arm64_dump_syscall(const char *tag, uint64_t cmd, + const struct regs_context * f_regs) +{ + svcinfo("SYSCALL %s: regs: %p cmd: %" PRId64 "\n", tag, f_regs, cmd); + + svcinfo("x0: 0x%-16lx x1: 0x%lx\n", + f_regs->regs[REG_X0], f_regs->regs[REG_X1]); + svcinfo("x2: 0x%-16lx x3: 0x%lx\n", + f_regs->regs[REG_X2], f_regs->regs[REG_X3]); + svcinfo("x4: 0x%-16lx x5: 0x%lx\n", + f_regs->regs[REG_X4], f_regs->regs[REG_X5]); + svcinfo("x6: 0x%-16lx x7: 0x%lx\n", + f_regs->regs[REG_X6], f_regs->regs[REG_X7]); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm64_syscall_switch + * + * Description: + * task swith syscall Review Comment: s/swith/switch/ ########## arch/arm64/src/common/arm64_head.S: ########## @@ -0,0 +1,291 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_head.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * DESCRIPTION + * Bring-up code for ARMv8. + * Based on head.S(arm64 porting) at Xen Hypervisor Project + * Based on reset.S(aarch64 porting) at Zephyr RTOS Project + * + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "arm64_arch.h" +#include "arm64_macro.inc" + +/* macro define from xen head, for efi head define */ +#define PAGE_SHIFT 12 +#define __HEAD_FLAG_PAGE_SIZE ((PAGE_SHIFT - 10) / 2) + +#define __HEAD_FLAG_PHYS_BASE 1 + + +#define __HEAD_FLAGS ((__HEAD_FLAG_PAGE_SIZE << 1) | \ + (__HEAD_FLAG_PHYS_BASE << 3)) + +#ifdef CONFIG_DEBUG_FEATURES + +#define RODATA_STR(label, msg) \ +.pushsection .rodata.str, "aMS", %progbits, 1 ; \ +label: .asciz msg; \ +.popsection + +/* Macro to print a string to the UART, if there is one. + * Clobbers x0 - x3, x30 is lr for return + */ +#define PRINT(_s) \ + mov x3, x30 ; \ + adr x1, 98f ; \ + bl boot_stage_puts; \ + mov x30, x3 ; \ + RODATA_STR(98, _s) +#else +#define PRINT(s) +#endif /* CONFIG_DEBUG_FEATURES */ + + /* Kernel startup entry point. + * --------------------------- + * + * The requirements are: + * MMU = off, D-cache = off, I-cache = on or off, + * x0 = physical address to the FDT blob. + * it will be used when NuttX support divice tree in the feature Review Comment: s/divice/device/ s/feature/future/ ########## arch/arm64/src/qemu/qemu_lowputc.S: ########## @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm64/src/qemu/qemu_lowputc.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + **************************************************************************** + * + * DESCRIPTION + * Wrapper for early printk + * + ***************************************************************************/ + +#include <nuttx/config.h> + +#include "arm64_macro.inc" + +/* 32-bit register definition for imx8qm uart */ + +#define UART1_BASE_ADDRESS 0x9000000 +#define EARLY_UART_PL011_BAUD_RATE 115200 + +/* PL011 UART initialization + * xb: register which containts the UART base address Review Comment: s/containts/contains/ -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: commits-unsubscr...@nuttx.apache.org For queries about this service, please contact Infrastructure at: us...@infra.apache.org
