gustavonihei commented on code in PR #6823: URL: https://github.com/apache/incubator-nuttx/pull/6823#discussion_r942389929
########## arch/xtensa/src/esp32s2/esp32s2_spi.c: ########## @@ -0,0 +1,1231 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#ifdef CONFIG_ESP32S2_SPI + +#include <assert.h> +#include <debug.h> +#include <sys/types.h> +#include <inttypes.h> +#include <stdint.h> +#include <stdbool.h> +#include <stdlib.h> +#include <time.h> + +#include <nuttx/arch.h> +#include <nuttx/irq.h> +#include <nuttx/clock.h> +#include <nuttx/semaphore.h> +#include <nuttx/spinlock.h> +#include <nuttx/spi/spi.h> + +#include <arch/board/board.h> + +#include "esp32s2_spi.h" +#include "esp32s2_irq.h" +#include "esp32s2_gpio.h" + +#include "xtensa.h" +#include "hardware/esp32s2_gpio_sigmap.h" +#include "hardware/esp32s2_pinmap.h" +#include "hardware/esp32s2_spi.h" +#include "hardware/esp32s2_soc.h" +#include "hardware/esp32s2_system.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check if Chip-Select pin will be controlled via software */ + +#ifdef CONFIG_ESP32S2_SPI_SWCS +# define SPI_HAVE_SWCS 1 +#else +# define SPI_HAVE_SWCS 0 +#endif + +/* SPI default frequency (limited by clock divider) */ + +#define SPI_DEFAULT_FREQ (400000) + +/* SPI default width */ + +#define SPI_DEFAULT_WIDTH (8) + +/* SPI default mode */ + +#define SPI_DEFAULT_MODE (SPIDEV_MODE0) + +/* Helper for applying the mask for a given register field. + * Mask is determined by the macros suffixed with _V and _S from the + * peripheral register description. + */ + +#define VALUE_MASK(_val, _field) (((_val) & (_field##_V)) << (_field##_S)) + +/* SPI Maximum buffer size in bytes */ + +#define SPI_MAX_BUF_SIZE (64) + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* SPI Device hardware configuration */ + +struct esp32s2_spi_config_s +{ + uint32_t clk_freq; /* SPI default clock frequency */ + uint32_t width; /* SPI default width */ + enum spi_mode_e mode; /* SPI default mode */ + + uint8_t id; /* ESP32-S2 SPI device ID: SPIx {2,3} */ + uint8_t cs_pin; /* GPIO configuration for CS */ + uint8_t mosi_pin; /* GPIO configuration for MOSI */ + uint8_t miso_pin; /* GPIO configuration for MISO */ + uint8_t clk_pin; /* GPIO configuration for CLK */ + uint32_t clk_bit; /* Clock enable bit */ + uint32_t rst_bit; /* SPI reset bit */ + uint32_t cs_insig; /* SPI CS input signal index */ + uint32_t cs_outsig; /* SPI CS output signal index */ + uint32_t mosi_insig; /* SPI MOSI input signal index */ + uint32_t mosi_outsig; /* SPI MOSI output signal index */ + uint32_t miso_insig; /* SPI MISO input signal index */ + uint32_t miso_outsig; /* SPI MISO output signal index */ + uint32_t clk_insig; /* SPI CLK input signal index */ + uint32_t clk_outsig; /* SPI CLK output signal index */ +}; + +struct esp32s2_spi_priv_s +{ + /* Externally visible part of the SPI interface */ + + struct spi_dev_s spi_dev; + + /* Port configuration */ + + const struct esp32s2_spi_config_s *config; + int refs; /* Reference count */ + sem_t exclsem; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + enum spi_mode_e mode; /* Actual SPI hardware mode */ + uint8_t nbits; /* Actual SPI send/receive bits once transmission */ + spinlock_t lock; /* Device specific lock. */ Review Comment: ```suggestion ``` Device-specific lock is not required for ESP32-S2, since it does not support SMP. -- This is an automated message from the Apache Git Service. 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