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commit c866b6be9ae5af8516b55008fe307810b4077def Author: ligd <[email protected]> AuthorDate: Thu Sep 15 22:10:12 2022 +0800 armv7a/r: add common operation CP15_SET/GET() Signed-off-by: ligd <[email protected]> --- arch/arm/src/armv7-a/arm_scu.c | 97 +------------ arch/arm/src/armv7-a/arm_timer.c | 80 ++--------- arch/arm/src/armv7-a/barriers.h | 2 + arch/arm/src/armv7-a/cp15.h | 72 +++++++++- arch/arm/src/armv7-a/cp15_cacheops.h | 169 +++++------------------ arch/arm/src/armv7-a/mmu.h | 116 ++++++---------- arch/arm/src/armv7-a/sctlr.h | 259 +++++++---------------------------- arch/arm/src/armv7-r/arm_timer.c | 80 ++--------- arch/arm/src/armv7-r/cp15.h | 82 +++++++++-- arch/arm/src/armv7-r/cp15_cacheops.h | 167 +++++----------------- arch/arm/src/armv7-r/mpu.h | 71 ++-------- arch/arm/src/armv7-r/sctlr.h | 257 ++++++++-------------------------- 12 files changed, 388 insertions(+), 1064 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c index 9f889ecfbf..2668e88896 100755 --- a/arch/arm/src/armv7-a/arm_scu.c +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -31,94 +31,7 @@ #include "barriers.h" #include "sctlr.h" #include "scu.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_get_sctlr - * - * Description: - * Get the contents of the SCTLR register - * - ****************************************************************************/ - -static inline uint32_t arm_get_sctlr(void) -{ - uint32_t sctlr; - - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c1, c0, 0\n" /* Read SCTLR */ - : "=r"(sctlr) - : - : - ); - - return sctlr; -} - -/**************************************************************************** - * Name: arm_set_sctlr - * - * Description: - * Set the contents of the SCTLR register - * - ****************************************************************************/ - -static inline void arm_set_sctlr(uint32_t sctlr) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c1, c0, 0\n" /* Write SCTLR */ - : - : "r"(sctlr) - : - ); -} - -/**************************************************************************** - * Name: arm_get_actlr - * - * Description: - * Get the contents of the ACTLR register - * - ****************************************************************************/ - -static inline uint32_t arm_get_actlr(void) -{ - uint32_t actlr; - - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c1, c0, 1\n" /* Read ACTLR */ - : "=r"(actlr) - : - : - ); - - return actlr; -} - -/**************************************************************************** - * Name: arm_set_actlr - * - * Description: - * Set the contents of the ACTLR register - * - ****************************************************************************/ - -static inline void arm_set_actlr(uint32_t actlr) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c1, c0, 1\n" /* Write ACTLR */ - : - : "r"(actlr) - : - ); -} +#include "cp15.h" /**************************************************************************** * Public Functions @@ -195,14 +108,14 @@ void arm_enable_smp(int cpu) * FW - Cache and TLB maintenance broadcast. */ - regval = arm_get_actlr(); + regval = CP15_GET(ACTLR); regval |= ACTLR_SMP; #ifdef CONFIG_ARCH_CORTEXA9 regval |= ACTLR_FW; #endif - arm_set_actlr(regval); + CP15_SET(ACTLR, regval); - regval = arm_get_sctlr(); + regval = CP15_GET(SCTLR); regval |= SCTLR_C | SCTLR_I | SCTLR_M; - arm_set_sctlr(regval); + CP15_SET(SCTLR, regval); } diff --git a/arch/arm/src/armv7-a/arm_timer.c b/arch/arm/src/armv7-a/arm_timer.c index 007030d2a5..0e86c2ca27 100644 --- a/arch/arm/src/armv7-a/arm_timer.c +++ b/arch/arm/src/armv7-a/arm_timer.c @@ -30,6 +30,7 @@ #include "arm_timer.h" #include "barriers.h" #include "gic.h" +#include "cp15.h" /**************************************************************************** * Pre-processor Definitions @@ -88,108 +89,43 @@ static const struct oneshot_operations_s g_arm_timer_ops = static inline uint32_t arm_timer_get_freq(void) { - uint32_t freq; - ARM_ISB(); - - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c14, c0, 0\n" /* Read CNTFRQ */ - : "=r"(freq) - : - : - ); - - return freq; + return CP15_GET(CNTFRQ); } static inline void arm_timer_set_freq(uint32_t freq) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c14, c0, 0\n" /* Write CNTFRQ */ - : - : "r"(freq) - : - ); - + CP15_SET(CNTFRQ, freq); ARM_ISB(); } static inline uint64_t arm_timer_get_count(void) { - uint64_t count; - ARM_ISB(); - - __asm__ __volatile__ - ( - "\tmrrc p15, 0, %Q0, %R0, c14\n" /* Read CNTPCT */ - : "=r"(count) - : - : - ); - - return count; + return CP15_GET64(CNTPCT); } static inline uint32_t arm_timer_get_ctrl(void) { - uint32_t ctrl; - ARM_ISB(); - - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c14, c2, 1\n" /* Read CNTP_CTL */ - : "=r"(ctrl) - : - : - ); - - return ctrl; + return CP15_GET(CNTP_CTL); } static inline void arm_timer_set_ctrl(uint32_t ctrl) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c14, c2, 1\n" /* Write CNTP_CTL */ - : - : "r"(ctrl) - : - ); - + CP15_SET(CNTP_CTL, ctrl); ARM_ISB(); } static inline uint32_t arm_timer_get_tval(void) { - uint32_t tval; - ARM_ISB(); - - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c14, c2, 0\n" /* Read CNTP_TVAL */ - : "=r"(tval) - : - : - ); - - return tval; + return CP15_GET(CNTP_TVAL); } static inline void arm_timer_set_tval(uint32_t tval) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c14, c2, 0\n" /* Write CNTP_TVAL */ - : - : "r"(tval) - : - ); - + CP15_SET(CNTP_TVAL, tval); ARM_ISB(); } diff --git a/arch/arm/src/armv7-a/barriers.h b/arch/arm/src/armv7-a/barriers.h index 70e98e5d48..b3a242c52f 100644 --- a/arch/arm/src/armv7-a/barriers.h +++ b/arch/arm/src/armv7-a/barriers.h @@ -34,9 +34,11 @@ #define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") #define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") #define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") +#define arm_nop(n) __asm__ __volatile__ ("nop\n") #define ARM_DSB() arm_dsb(15) #define ARM_ISB() arm_isb(15) #define ARM_DMB() arm_dmb(15) +#define ARM_NOP() arm_nop(15) #endif /* __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H */ diff --git a/arch/arm/src/armv7-a/cp15.h b/arch/arm/src/armv7-a/cp15.h index 47da92da89..587e883e6a 100644 --- a/arch/arm/src/armv7-a/cp15.h +++ b/arch/arm/src/armv7-a/cp15.h @@ -58,7 +58,13 @@ * Reference: Cortex-A5� MPCore, Technical Reference Manual, Paragraph 4.2. */ -#define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2 +#ifdef __ASSEMBLY__ +# define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2 +# define _CP15_64(op1,lo,hi,op2) p15, op1, lo, hi, op2 +#else +# define _CP15(op1,rd,crn,crm,op2) "p15, " #op1 ", %0, " #crn ", " #crm ", " #op2 +# define _CP15_64(op1,lo,hi,op2) "p15, " #op1 ", %Q0, %R0, " #op2 +#endif #define CP15_MIDR(r) _CP15(0, r, c0, c0, 0) /* Main ID Register */ #define CP15_CTR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */ @@ -182,6 +188,15 @@ #define CP15_TPIDRURO(r) _CP15(0, r, c13, c0, 3) #define CP15_TPIDRPRW(r) _CP15(0, r, c13, c0, 4) +#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */ +#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */ +#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */ +#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 1) /* PL1 Physical Timer Control register */ +#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */ +#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */ + +#define CP15_CNTPCT(lo,hi) _CP15_64(0, lo, hi, c14) /* Physical Count register */ + #define CP15_PWRCTRL(r) _CP15(0, r, c15, c0, 0) /* Power Control Register (Cortex-A9) */ #define CP15_NEONBUSY(r) _CP15(0, r, c15, c1, 1) /* NEON Busy Register (Cortex-A9) */ #define CP15_DR0(r) _CP15(3, r, c15, c0, 0) /* Data Register (Cortex-A5) */ @@ -199,4 +214,59 @@ #define CP15_MAINTLBPA(r) _CP15(5, r, c15, c6, 2) /* Main TLB PA register (Cortex-A9) */ #define CP15_MAINTLBAT(r) _CP15(5, r, c15, c7, 2) /* Main TLB Attribute register (Cortex-A9) */ +#define CP15_SET(reg, value) \ + do \ + { \ + __asm__ __volatile__ \ + ( \ + "mcr " CP15_ ## reg(0) "\n" \ + :: "r"(value): "memory" \ + ); \ + } \ + while(0) \ + +#define CP15_SET2(reg, op, value) \ + do \ + { \ + __asm__ __volatile__ \ + ( \ + "mcr " CP15_ ## reg(0, op) "\n" \ + :: "r"(value): "memory" \ + ); \ + } \ + while(0) \ + +#define CP15_GET(reg) \ + ({ \ + uint32_t value; \ + __asm__ __volatile__ \ + ( \ + "mrc " CP15_ ## reg(0) "\n" \ + : "=r"(value) :: "memory" \ + ); \ + value; \ + }) \ + +#define CP15_SET64(reg, value) \ + do \ + { \ + __asm__ __volatile__ \ + ( \ + "mcrr " CP15_ ## reg(0,0) "\n" \ + :: "r"(value): "memory" \ + ); \ + } \ + while(0) \ + +#define CP15_GET64(reg) \ + ({ \ + uint64_t value; \ + __asm__ __volatile__ \ + ( \ + "mrrc " CP15_ ## reg(0,0) "\n" \ + : "=r"(value) :: "memory" \ + ); \ + value; \ + }) \ + #endif /* __ARCH_ARM_SRC_ARMV7_A_CP15_H */ diff --git a/arch/arm/src/armv7-a/cp15_cacheops.h b/arch/arm/src/armv7-a/cp15_cacheops.h index 18fad4d8c1..cf827c88d8 100644 --- a/arch/arm/src/armv7-a/cp15_cacheops.h +++ b/arch/arm/src/armv7-a/cp15_cacheops.h @@ -55,6 +55,8 @@ * Included Files ****************************************************************************/ +#include "sctlr.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -324,7 +326,7 @@ * * Description: * Invalidate all instruction caches to PoU, also flushes branch target - * cache + * cache * * Input Parameters: * None @@ -545,15 +547,11 @@ static inline void cp15_enable_dcache(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\torr r0, r0, #(1 << 2)\n" /* Enable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr |= SCTLR_C; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -572,15 +570,11 @@ static inline void cp15_enable_dcache(void) static inline void cp15_disable_dcache(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr &= ~SCTLR_C; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -599,15 +593,11 @@ static inline void cp15_disable_dcache(void) static inline void cp15_enable_icache(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\torr r0, r0, #(1 << 12)\n" /* Enable I cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr |= SCTLR_I; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -626,15 +616,11 @@ static inline void cp15_enable_icache(void) static inline void cp15_disable_icache(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr &= ~SCTLR_I; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -653,14 +639,7 @@ static inline void cp15_disable_icache(void) static inline void cp15_invalidate_icache_inner_sharable(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c1, 0\n" /* ICIALLUIS */ - : - : - : "r0", "memory" - ); + CP15_SET(ICIALLUIS, 0); } /**************************************************************************** @@ -679,14 +658,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void) static inline void cp15_invalidate_btb_inner_sharable(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */ - : - : - : "r0", "memory" - ); + CP15_SET(BPIALLIS, 0); } /**************************************************************************** @@ -706,14 +678,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void) static inline void cp15_invalidate_icache(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 0\n" /* ICIALLU */ - : - : - : "r0", "memory" - ); + CP15_SET(ICIALLU, 0); } /**************************************************************************** @@ -732,13 +697,7 @@ static inline void cp15_invalidate_icache(void) static inline void cp15_invalidate_icache_bymva(unsigned int va) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c5, 1\n" /* ICIMVAU */ - : - : "r" (va) - : "memory" - ); + CP15_SET(ICIMVAU, va); } /**************************************************************************** @@ -757,14 +716,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va) static inline void cp15_flush_btb(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */ - : - : - : "r0", "memory" - ); + CP15_SET(BPIALL, 0); } /**************************************************************************** @@ -783,14 +735,7 @@ static inline void cp15_flush_btb(void) static inline void cp15_flush_btb_bymva(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 7\n" /* BPIMVA */ - : - : - : "r0", "memory" - ); + CP15_SET(BPIMVA, 0); } /**************************************************************************** @@ -811,13 +756,7 @@ static inline void cp15_flush_btb_bymva(void) static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c6, 1\n" /* DCIMVAC */ - : - : "r" (va) - : "memory" - ); + CP15_SET(DCIMVAC, va); } /**************************************************************************** @@ -838,13 +777,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c6, 2\n" /* DCISW */ - : - : "r" (setway) - : "memory" - ); + CP15_SET(DCISW, setway); } /**************************************************************************** @@ -865,13 +798,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) static inline void cp15_clean_dcache_bymva(unsigned int va) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c10, 1\n" /* DCCMVAC */ - : - : "r" (va) - : "memory" - ); + CP15_SET(DCCMVAC, va); } /**************************************************************************** @@ -890,13 +817,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va) static inline void cp15_clean_dcache_bysetway(unsigned int setway) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c10, 2\n" /* DCCSW */ - : - : "r" (setway) - : "memory" - ); + CP15_SET(DCCSW, setway); } /**************************************************************************** @@ -915,13 +836,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway) static inline void cp15_clean_ucache_bymva(unsigned int setway) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c11, 1\n" /* DCCMVAU */ - : - : "r" (setway) - : "memory" - ); + CP15_SET(DCCMVAU, setway); } /**************************************************************************** @@ -940,13 +855,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int setway) static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, r0, c7, c14, 1\n" /* DCCIMVAC */ - : - : "r" (va) - : "memory" - ); + CP15_SET(DCCIMVAC, va); } /**************************************************************************** @@ -965,13 +874,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c14, 2\n" /* DCCISW */ - : - : "r" (setway) - : "memory" - ); + CP15_SET(DCCISW, setway); } #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index a6e9b54dd3..093a56018e 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -35,10 +35,12 @@ #include <nuttx/config.h> #include <sys/types.h> +#include "sctlr.h" #ifndef __ASSEMBLY__ # include <stdint.h> # include "chip.h" +# include "barriers.h" #endif /* __ASSEMBLY__ */ /**************************************************************************** @@ -1195,15 +1197,11 @@ struct section_mapping_s static inline void cp15_disable_mmu(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" - "\tbic r0, r0, #1\n" - "\tmcr p15, 0, r0, c1, c0, 0\n" - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr &= ~SCTLR_M; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -1225,22 +1223,16 @@ static inline void cp15_disable_mmu(void) static inline void cp15_invalidate_tlbs(void) { - __asm__ __volatile__ - ( - "\tdsb\n" + ARM_DSB(); #ifdef CONFIG_ARM_HAVE_MPCORE - "\tmcr p15, 0, r0, c8, c3, 0\n" /* TLBIALLIS */ - "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */ + CP15_SET(TLBIALLIS, 0); + CP15_SET(BPIALLIS, 0); #else - "\tmcr p15, 0, r0, c8, c7, 0\n" /* TLBIALL */ - "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */ + CP15_SET2(TLBIALL, c7, 0); + CP15_SET(BPIALL, 0); #endif - "\tdsb\n" - "\tisb\n" - : - : - : "r0", "memory" - ); + ARM_DSB(); + ARM_ISB(); } /**************************************************************************** @@ -1256,22 +1248,16 @@ static inline void cp15_invalidate_tlbs(void) static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr) { - __asm__ __volatile__ - ( - "\tdsb\n" + ARM_DSB(); #ifdef CONFIG_ARM_HAVE_MPCORE - "\tmcr p15, 0, %0, c8, c3, 3\n" /* TLBIMVAAIS */ - "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */ + CP15_SET(TLBIMVAAIS, vaddr); + CP15_SET(BPIALLIS, 0); #else - "\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */ - "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */ + CP15_SET2(TLBIMVA, c7, vaddr); + CP15_SET(BPIALL, 0); #endif - "\tdsb\n" - "\tisb\n" - : - : "r" (vaddr) - : "r1", "memory" - ); + ARM_DSB(); + ARM_ISB(); } /**************************************************************************** @@ -1287,21 +1273,15 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr) static inline void cp15_wrdacr(unsigned int dacr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c3, c0, 0\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - : - : "r" (dacr) - : "memory" - ); + CP15_SET(DACR, dacr); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); } /**************************************************************************** @@ -1321,23 +1301,16 @@ static inline void cp15_wrdacr(unsigned int dacr) static inline void cp15_wrttb(unsigned int ttb) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c2, c0, 0\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tmov r1, #0\n" - "\tmcr p15, 0, r1, c2, c0, 2\n" - : - : "r" (ttb) - : "r1", "memory" - ); + CP15_SET(TTBR0, ttb); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + CP15_SET(TTBCR, 0); } /**************************************************************************** @@ -1359,14 +1332,7 @@ static inline uint32_t *mmu_l1_pgtable(void) uint32_t ttbr0; uint32_t pgtable; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c2, c0, 0\n" - : "=r" (ttbr0) - : - : - ); - + ttbr0 = CP15_GET(TTBR0); pgtable = ttbr0 & TTBR0_BASE_MASK(0); return (uint32_t *)(pgtable - PGTABLE_BASE_PADDR + PGTABLE_BASE_VADDR); #else diff --git a/arch/arm/src/armv7-a/sctlr.h b/arch/arm/src/armv7-a/sctlr.h index cd8c52d627..6d12e49167 100644 --- a/arch/arm/src/armv7-a/sctlr.h +++ b/arch/arm/src/armv7-a/sctlr.h @@ -34,6 +34,9 @@ * Included Files ****************************************************************************/ +#include "barriers.h" +#include "cp15.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -455,94 +458,58 @@ static inline unsigned int cp15_rdid(void) { - unsigned int id; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c0, c0, 0\n" - : "=r" (id) - : - : "memory" - ); - - return id; + return CP15_GET(MIDR); } /* Get the Multiprocessor Affinity Register (MPIDR) */ static inline unsigned int cp15_rdmpidr(void) { - unsigned int mpidr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c0, c0, 5\n" - : "=r" (mpidr) - : - : "memory" - ); - - return mpidr; + return CP15_GET(MPIDR); } /* Read/write the system control register (SCTLR) */ static inline unsigned int cp15_rdsctlr(void) { - unsigned int sctlr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c1, c0, 0\n" - : "=r" (sctlr) - : - : "memory" - ); - - return sctlr; + return CP15_GET(SCTLR); } static inline void cp15_wrsctlr(unsigned int sctlr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c1, c0, 0\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - : - : "r" (sctlr) - : "memory" - ); + CP15_SET(SCTLR, sctlr); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); } /* Read/write the vector base address register (VBAR) */ static inline unsigned int cp15_rdvbar(void) { - unsigned int sctlr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c12, c0, 0\n" - : "=r" (sctlr) - : - : "memory" - ); + return CP15_GET(VBAR); +} + +static inline void cp15_wrvbar(unsigned int vbar) +{ + CP15_SET(VBAR, vbar); +} + +/* Read/write the implementation defined Auxiliary Control Register (ACTLR) */ - return sctlr; +static inline unsigned int cp15_rdactlr(void) +{ + return CP15_GET(ACTLR); } -static inline void cp15_wrvbar(unsigned int sctlr) +static inline void cp15_wractlr(unsigned int actlr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c12, c0, 0\n" - : - : "r" (sctlr) - : "memory" - ); + CP15_SET(ACTLR, actlr); } /**************************************************************************** @@ -555,27 +522,12 @@ static inline void cp15_wrvbar(unsigned int sctlr) static inline unsigned int cp15_pmu_rdpmcr(void) { - unsigned int pmcr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 0\n" - : "=r" (pmcr) - : - : "memory" - ); - - return pmcr; + return CP15_GET(PMCR); } static inline void cp15_pmu_wrpmcr(unsigned int pmcr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 0\n" - : - : "r" (pmcr) - : "memory" - ); + CP15_SET(PMCR, pmcr); } static inline void cp15_pmu_pmcr(unsigned int pmcr) @@ -594,27 +546,12 @@ static inline void cp15_pmu_pmcr(unsigned int pmcr) static inline unsigned int cp15_pmu_rdcesr(void) { - unsigned int cesr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 1\n" - : "=r" (cesr) - : - : "memory" - ); - - return cesr; + return CP15_GET(PMCNTENSET); } static inline void cp15_pmu_wrcesr(unsigned int cesr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 1\n" - : - : "r" (cesr) - : "memory" - ); + CP15_SET(PMCNTENSET, cesr); } static inline void cp15_pmu_cesr(unsigned int cesr) @@ -633,27 +570,12 @@ static inline void cp15_pmu_cesr(unsigned int cesr) static inline unsigned int cp15_pmu_rdcecr(void) { - unsigned int cecr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 2\n" - : "=r" (cecr) - : - : "memory" - ); - - return cecr; + return CP15_GET(PMCNTENCLR); } static inline void cp15_pmu_wrcecr(unsigned int cecr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 2\n" - : - : "r" (cecr) - : "memory" - ); + CP15_SET(PMCNTENCLR, cecr); } static inline void cp15_pmu_cecr(unsigned int cecr) @@ -672,27 +594,12 @@ static inline void cp15_pmu_cecr(unsigned int cecr) static inline unsigned int cp15_pmu_rdofsr(void) { - unsigned int ofsr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 3\n" - : "=r" (ofsr) - : - : "memory" - ); - - return ofsr; + return CP15_GET(PMOVSR); } static inline void cp15_pmu_wrofsr(unsigned int ofsr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 3\n" - : - : "r" (ofsr) - : "memory" - ); + CP15_SET(PMOVSR, ofsr); } static inline void cp15_pmu_ofsr(unsigned int ofsr) @@ -711,27 +618,12 @@ static inline void cp15_pmu_ofsr(unsigned int ofsr) static inline unsigned int cp15_pmu_rdsir(void) { - unsigned int sir; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 4\n" - : "=r" (sir) - : - : "memory" - ); - - return sir; + return CP15_GET(PMSWINC); } static inline void cp15_pmu_wrsir(unsigned int sir) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 4\n" - : - : "r" (sir) - : "memory" - ); + CP15_SET(PMSWINC, sir); } static inline void cp15_pmu_sir(unsigned int sir) @@ -749,13 +641,7 @@ static inline void cp15_pmu_sir(unsigned int sir) static inline void cp15_pmu_wrecsr(unsigned int ecsr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 5\n" - : - : "r" (ecsr) - : "memory" - ); + CP15_SET(PMSELR, ecsr); } /**************************************************************************** @@ -768,13 +654,7 @@ static inline void cp15_pmu_wrecsr(unsigned int ecsr) static inline void cp15_pmu_wretsr(unsigned int etsr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c13, 1\n" - : - : "r" (etsr) - : "memory" - ); + CP15_SET(PMXEVTYPER, etsr); } /**************************************************************************** @@ -787,27 +667,12 @@ static inline void cp15_pmu_wretsr(unsigned int etsr) static inline unsigned int cp15_pmu_rduer(void) { - unsigned int uer; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c14, 0\n" - : "=r" (uer) - : - : "memory" - ); - - return uer; + return CP15_GET(PMUSERENR); } static inline void cp15_pmu_wruer(unsigned int uer) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c14, 0\n" - : - : "r" (uer) - : "memory" - ); + CP15_SET(PMUSERENR, uer); } static inline void cp15_pmu_uer(unsigned int uer) @@ -826,13 +691,7 @@ static inline void cp15_pmu_uer(unsigned int uer) static inline void cp15_pmu_wriesr(unsigned int iesr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c14, 1\n" - : - : "r" (iesr) - : "memory" - ); + CP15_SET(PMINTENSET, iesr); } /**************************************************************************** @@ -846,13 +705,7 @@ static inline void cp15_pmu_wriesr(unsigned int iesr) static inline void cp15_pmu_wriecr(unsigned int iecr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c14, 2\n" - : - : "r" (iecr) - : "memory" - ); + CP15_SET(PMINTENCLR, iecr); } /**************************************************************************** @@ -865,16 +718,7 @@ static inline void cp15_pmu_wriecr(unsigned int iecr) static inline unsigned int cp15_pmu_rdccr(void) { - unsigned int ccr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c13, 0\n" - : "=r" (ccr) - : - : "memory" - ); - - return ccr; + return CP15_GET(PMCCNTR); } /**************************************************************************** @@ -887,16 +731,7 @@ static inline unsigned int cp15_pmu_rdccr(void) static inline unsigned int cp15_pmu_rdecr(void) { - unsigned int ecr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c13, 2" - : "=r" (ecr) - : - : "memory" - ); - - return ecr; + return CP15_GET(PMXEVCNTR); } #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv7-r/arm_timer.c b/arch/arm/src/armv7-r/arm_timer.c index 42c5e6d95e..2486d90f2c 100644 --- a/arch/arm/src/armv7-r/arm_timer.c +++ b/arch/arm/src/armv7-r/arm_timer.c @@ -30,6 +30,7 @@ #include "arm_timer.h" #include "barriers.h" #include "gic.h" +#include "cp15.h" /**************************************************************************** * Pre-processor Definitions @@ -88,108 +89,43 @@ static const struct oneshot_operations_s g_arm_timer_ops = static inline uint32_t arm_timer_get_freq(void) { - uint32_t freq; - ARM_ISB(); - - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c14, c0, 0\n" /* Read CNTFRQ */ - : "=r"(freq) - : - : - ); - - return freq; + return CP15_GET(CNTFRQ); } static inline void arm_timer_set_freq(uint32_t freq) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c14, c0, 0\n" /* Write CNTFRQ */ - : - : "r"(freq) - : - ); - + CP15_SET(CNTFRQ, freq); ARM_ISB(); } static inline uint64_t arm_timer_get_count(void) { - uint64_t count; - ARM_ISB(); - - __asm__ __volatile__ - ( - "\tmrrc p15, 0, %Q0, %R0, c14\n" /* Read CNTPCT */ - : "=r"(count) - : - : - ); - - return count; + return CP15_GET64(CNTPCT); } static inline uint32_t arm_timer_get_ctrl(void) { - uint32_t ctrl; - ARM_ISB(); - - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c14, c2, 1\n" /* Read CNTP_CTL */ - : "=r"(ctrl) - : - : - ); - - return ctrl; + return CP15_GET(CNTP_CTL); } static inline void arm_timer_set_ctrl(uint32_t ctrl) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c14, c2, 1\n" /* Write CNTP_CTL */ - : - : "r"(ctrl) - : - ); - + CP15_SET(CNTP_CTL, ctrl); ARM_ISB(); } static inline uint32_t arm_timer_get_tval(void) { - uint32_t tval; - ARM_ISB(); - - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c14, c2, 0\n" /* Read CNTP_TVAL */ - : "=r"(tval) - : - : - ); - - return tval; + return CP15_GET(CNTP_TVAL); } static inline void arm_timer_set_tval(uint32_t tval) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c14, c2, 0\n" /* Write CNTP_TVAL */ - : - : "r"(tval) - : - ); - + CP15_SET(CNTP_TVAL, tval); ARM_ISB(); } diff --git a/arch/arm/src/armv7-r/cp15.h b/arch/arm/src/armv7-r/cp15.h index 4c5bd42698..b51ac20d4b 100644 --- a/arch/arm/src/armv7-r/cp15.h +++ b/arch/arm/src/armv7-r/cp15.h @@ -55,7 +55,13 @@ * Reference: Cortex-A5� MPCore, Technical Reference Manual, Paragraph 4.2. */ -#define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2 +#ifdef __ASSEMBLY__ +# define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2 +# define _CP15_64(op1,lo,hi,op2) p15, op1, lo, hi, op2 +#else +# define _CP15(op1,rd,crn,crm,op2) "p15, " #op1 ", %0, " #crn ", " #crm ", " #op2 +# define _CP15_64(op1,lo,hi,op2) "p15, " #op1 ", %Q0, %R0, " #op2 +#endif #define CP15_MIDR(r) _CP15(0, r, c0, c0, 0) /* Main ID Register */ #define CP15_CTR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */ @@ -141,16 +147,70 @@ #define CP15_TPIDRURO(r) _CP15(0, r, c13, c0, 3) #define CP15_TPIDRPRW(r) _CP15(0, r, c13, c0, 4) -#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */ -#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */ -#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */ -#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical Timer Control register */ -#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */ -#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */ -#define CP15_CNTPCT(r,n) _CP15(0, r, c14, c14, n) /* 64-bit Physical Count register */ -#define CP15_CNTVCT(r,n) _CP15(1, r, c14, c14, n) /* Virtual Count register */ -#define CP15_CNTP_CVAL(r,n) _CP15(2, r, c14, c14, n) /* PL1 Physical Timer CompareValue register */ -#define CP15_CNTV_CVAL(r,n) _CP15(3, r, c14, c14, n) /* Virtual Timer CompareValue register */ +#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */ +#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */ +#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */ +#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 1) /* PL1 Physical Timer Control register */ +#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */ +#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */ + +#define CP15_CNTPCT(lo,hi) _CP15_64(0, lo, hi, c14) /* Physical Count register */ + #define CP15_DCIALLU(r) _CP15(0, r, c15, c5, 0) /* Invalidate data cache */ +#define CP15_SET(reg, value) \ + do \ + { \ + __asm__ __volatile__ \ + ( \ + "mcr " CP15_ ## reg(0) "\n" \ + :: "r"(value): "memory" \ + ); \ + } \ + while(0) \ + +#define CP15_SET2(reg, op, value) \ + do \ + { \ + __asm__ __volatile__ \ + ( \ + "mcr " CP15_ ## reg(0, op) "\n" \ + :: "r"(value): "memory" \ + ); \ + } \ + while(0) \ + +#define CP15_GET(reg) \ + ({ \ + uint32_t value; \ + __asm__ __volatile__ \ + ( \ + "mrc " CP15_ ## reg(0) "\n" \ + : "=r"(value) :: "memory" \ + ); \ + value; \ + }) \ + +#define CP15_SET64(reg, value) \ + do \ + { \ + __asm__ __volatile__ \ + ( \ + "mcrr " CP15_ ## reg(0,0) "\n" \ + :: "r"(value): "memory" \ + ); \ + } \ + while(0) \ + +#define CP15_GET64(reg) \ + ({ \ + uint64_t value; \ + __asm__ __volatile__ \ + ( \ + "mrrc " CP15_ ## reg(0,0) "\n" \ + : "=r"(value) :: "memory" \ + ); \ + value; \ + }) \ + #endif /* __ARCH_ARM_SRC_ARMV7_R_CP15_H */ diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h index 7d0bfdc7a8..1be45e32e4 100644 --- a/arch/arm/src/armv7-r/cp15_cacheops.h +++ b/arch/arm/src/armv7-r/cp15_cacheops.h @@ -53,6 +53,8 @@ * Included Files ****************************************************************************/ +#include "sctlr.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -552,15 +554,11 @@ static inline void cp15_enable_dcache(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\torr r0, r0, #(1 << 2)\n" /* Enable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr |= SCTLR_C; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -579,15 +577,11 @@ static inline void cp15_enable_dcache(void) static inline void cp15_disable_dcache(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr &= ~SCTLR_C; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -606,15 +600,11 @@ static inline void cp15_disable_dcache(void) static inline void cp15_enable_icache(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\torr r0, r0, #(1 << 12)\n" /* Enable I cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr |= SCTLR_I; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -633,15 +623,11 @@ static inline void cp15_enable_icache(void) static inline void cp15_disable_icache(void) { - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); + uint32_t sctlr; + + sctlr = CP15_GET(SCTLR); + sctlr &= ~SCTLR_I; + CP15_SET(SCTLR, sctlr); } /**************************************************************************** @@ -660,14 +646,7 @@ static inline void cp15_disable_icache(void) static inline void cp15_invalidate_icache_inner_sharable(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c1, 0\n" /* ICIALLUIS */ - : - : - : "r0", "memory" - ); + CP15_SET(ICIALLUIS, 0); } /**************************************************************************** @@ -686,14 +665,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void) static inline void cp15_invalidate_btb_inner_sharable(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */ - : - : - : "r0", "memory" - ); + CP15_SET(BPIALLIS, 0); } /**************************************************************************** @@ -713,14 +685,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void) static inline void cp15_invalidate_icache(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 0\n" /* ICIALLU */ - : - : - : "r0", "memory" - ); + CP15_SET(ICIALLU, 0); } /**************************************************************************** @@ -739,13 +704,7 @@ static inline void cp15_invalidate_icache(void) static inline void cp15_invalidate_icache_bymva(unsigned int va) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c5, 1\n" /* ICIMVAU */ - : - : "r" (va) - : "memory" - ); + CP15_SET(ICIMVAU, va); } /**************************************************************************** @@ -764,14 +723,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va) static inline void cp15_flush_btb(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */ - : - : - : "r0", "memory" - ); + CP15_SET(BPIALL, 0); } /**************************************************************************** @@ -790,14 +742,7 @@ static inline void cp15_flush_btb(void) static inline void cp15_flush_btb_bymva(void) { - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 7\n" /* BPIMVA */ - : - : - : "r0", "memory" - ); + CP15_SET(BPIMVA, 0); } /**************************************************************************** @@ -818,13 +763,7 @@ static inline void cp15_flush_btb_bymva(void) static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c6, 1\n" /* DCIMVAC */ - : - : "r" (va) - : "memory" - ); + CP15_SET(DCIMVAC, va); } /**************************************************************************** @@ -845,13 +784,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c6, 2\n" /* DCISW */ - : - : "r" (setway) - : "memory" - ); + CP15_SET(DCISW, setway); } /**************************************************************************** @@ -872,13 +805,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) static inline void cp15_clean_dcache_bymva(unsigned int va) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c10, 1\n" /* DCCMVAC */ - : - : "r" (va) - : "memory" - ); + CP15_SET(DCCMVAC, va); } /**************************************************************************** @@ -897,13 +824,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va) static inline void cp15_clean_dcache_bysetway(unsigned int setway) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c10, 2\n" /* DCCSW */ - : - : "r" (setway) - : "memory" - ); + CP15_SET(DCCSW, setway); } /**************************************************************************** @@ -922,13 +843,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway) static inline void cp15_clean_ucache_bymva(unsigned int setway) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c11, 1\n" /* DCCMVAU */ - : - : "r" (setway) - : "memory" - ); + CP15_SET(DCCMVAU, setway); } /**************************************************************************** @@ -947,13 +862,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int setway) static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, r0, c7, c14, 1\n" /* DCCIMVAC */ - : - : "r" (va) - : "memory" - ); + CP15_SET(DCCIMVAC, va); } /**************************************************************************** @@ -972,13 +881,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c14, 2\n" /* DCCISW */ - : - : "r" (setway) - : "memory" - ); + CP15_SET(DCCISW, setway); } #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 5029b12fdc..e7e05d7a59 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -215,16 +215,7 @@ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size); static inline unsigned int mpu_get_mpuir(void) { - unsigned int mpuir; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c0, c0, 4" - : "=r" (mpuir) - : - : "memory" - ); - - return mpuir; + return CP15_GET(MPUIR); } /**************************************************************************** @@ -237,13 +228,7 @@ static inline unsigned int mpu_get_mpuir(void) static inline void mpu_set_drbar(unsigned int drbar) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c6, c1, 0" - : - : "r" (drbar) - : "memory" - ); + CP15_SET(DRBAR, drbar); } /**************************************************************************** @@ -256,13 +241,7 @@ static inline void mpu_set_drbar(unsigned int drbar) static inline void mpu_set_drsr(unsigned int drsr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c6, c1, 2" - : - : "r" (drsr) - : "memory" - ); + CP15_SET(DRSR, drsr); } /**************************************************************************** @@ -275,13 +254,7 @@ static inline void mpu_set_drsr(unsigned int drsr) static inline void mpu_set_dracr(unsigned int dracr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c6, c1, 4" - : - : "r" (dracr) - : "memory" - ); + CP15_SET(DRACR, dracr); } /**************************************************************************** @@ -295,13 +268,7 @@ static inline void mpu_set_dracr(unsigned int dracr) #ifndef CONFIG_ARM_HAVE_MPU_UNIFIED static inline void mpu_set_irbar(unsigned int irbar) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c6, c1, 1" - : - : "r" (irbar) - : "memory" - ); + CP15_SET(IRBAR, irbar); } #endif @@ -316,13 +283,7 @@ static inline void mpu_set_irbar(unsigned int irbar) #ifndef CONFIG_ARM_HAVE_MPU_UNIFIED static inline void mpu_set_irsr(unsigned int irsr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c6, c1, 3" - : - : "r" (irsr) - : "memory" - ); + CP15_SET(IRSR, irsr); } #endif @@ -330,20 +291,14 @@ static inline void mpu_set_irsr(unsigned int irsr) * Name: mpu_set_iracr * * Description: - * Write to the IRCR register + * Write to the IRACR register * ****************************************************************************/ #ifndef CONFIG_ARM_HAVE_MPU_UNIFIED static inline void mpu_set_iracr(unsigned int iracr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c6, c1, 5" - : - : "r" (iracr) - : "memory" - ); + CP15_SET(IRACR, iracr); } #endif @@ -351,19 +306,13 @@ static inline void mpu_set_iracr(unsigned int iracr) * Name: mpu_set_rgnr * * Description: - * Write to the IRCR register + * Write to the RGNR register * ****************************************************************************/ static inline void mpu_set_rgnr(unsigned int rgnr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c6, c2, 0" - : - : "r" (rgnr) - : "memory" - ); + CP15_SET(RGNR, rgnr); } /**************************************************************************** diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h index b5497f96cc..78c589e03c 100644 --- a/arch/arm/src/armv7-r/sctlr.h +++ b/arch/arm/src/armv7-r/sctlr.h @@ -32,6 +32,9 @@ * Included Files ****************************************************************************/ +#include "barriers.h" +#include "cp15.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -492,82 +495,62 @@ #ifndef __ASSEMBLY__ -/* Get the device ID */ +/* Get the device ID register */ static inline unsigned int cp15_rdid(void) { - unsigned int id; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c0, c0, 0" - : "=r" (id) - : - : "memory" - ); + return CP15_GET(MIDR); +} - return id; +/* Get the Multiprocessor Affinity Register (MPIDR) */ + +static inline unsigned int cp15_rdmpidr(void) +{ + return CP15_GET(MPIDR); } /* Read/write the system control register (SCTLR) */ static inline unsigned int cp15_rdsctlr(void) { - unsigned int sctlr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c1, c0, 0\n" - : "=r" (sctlr) - : - : "memory" - ); - - return sctlr; + return CP15_GET(SCTLR); } static inline void cp15_wrsctlr(unsigned int sctlr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c1, c0, 0\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - "\tnop\n" - : - : "r" (sctlr) - : "memory" - ); + CP15_SET(SCTLR, sctlr); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); + ARM_NOP(); +} + +/* Read/write the vector base address register (VBAR) */ + +static inline unsigned int cp15_rdvbar(void) +{ + return CP15_GET(VBAR); +} + +static inline void cp15_wrvbar(unsigned int vbar) +{ + CP15_SET(VBAR, vbar); } /* Read/write the implementation defined Auxiliary Control Register (ACTLR) */ static inline unsigned int cp15_rdactlr(void) { - unsigned int actlr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c1, c0, 1\n" - : "=r" (actlr) - : - : "memory" - ); - - return actlr; + return CP15_GET(ACTLR); } static inline void cp15_wractlr(unsigned int actlr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c1, c0, 1\n" - : - : "r" (actlr) - : "memory" - ); + CP15_SET(ACTLR, actlr); } /**************************************************************************** @@ -580,27 +563,12 @@ static inline void cp15_wractlr(unsigned int actlr) static inline unsigned int cp15_pmu_rdpmcr(void) { - unsigned int pmcr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 0\n" - : "=r" (pmcr) - : - : "memory" - ); - - return pmcr; + return CP15_GET(PMCR); } static inline void cp15_pmu_wrpmcr(unsigned int pmcr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 0\n" - : - : "r" (pmcr) - : "memory" - ); + CP15_SET(PMCR, pmcr); } static inline void cp15_pmu_pmcr(unsigned int pmcr) @@ -619,27 +587,12 @@ static inline void cp15_pmu_pmcr(unsigned int pmcr) static inline unsigned int cp15_pmu_rdcesr(void) { - unsigned int cesr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 1\n" - : "=r" (cesr) - : - : "memory" - ); - - return cesr; + return CP15_GET(PMCNTENSET); } static inline void cp15_pmu_wrcesr(unsigned int cesr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 1\n" - : - : "r" (cesr) - : "memory" - ); + CP15_SET(PMCNTENSET, cesr); } static inline void cp15_pmu_cesr(unsigned int cesr) @@ -658,27 +611,12 @@ static inline void cp15_pmu_cesr(unsigned int cesr) static inline unsigned int cp15_pmu_rdcecr(void) { - unsigned int cecr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 2\n" - : "=r" (cecr) - : - : "memory" - ); - - return cecr; + return CP15_GET(PMCNTENCLR); } static inline void cp15_pmu_wrcecr(unsigned int cecr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 2\n" - : - : "r" (cecr) - : "memory" - ); + CP15_SET(PMCNTENCLR, cecr); } static inline void cp15_pmu_cecr(unsigned int cecr) @@ -697,27 +635,12 @@ static inline void cp15_pmu_cecr(unsigned int cecr) static inline unsigned int cp15_pmu_rdofsr(void) { - unsigned int ofsr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 3\n" - : "=r" (ofsr) - : - : "memory" - ); - - return ofsr; + return CP15_GET(PMOVSR); } static inline void cp15_pmu_wrofsr(unsigned int ofsr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 3\n" - : - : "r" (ofsr) - : "memory" - ); + CP15_SET(PMOVSR, ofsr); } static inline void cp15_pmu_ofsr(unsigned int ofsr) @@ -736,27 +659,12 @@ static inline void cp15_pmu_ofsr(unsigned int ofsr) static inline unsigned int cp15_pmu_rdsir(void) { - unsigned int sir; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c12, 4\n" - : "=r" (sir) - : - : "memory" - ); - - return sir; + return CP15_GET(PMSWINC); } static inline void cp15_pmu_wrsir(unsigned int sir) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 4\n" - : - : "r" (sir) - : "memory" - ); + CP15_SET(PMSWINC, sir); } static inline void cp15_pmu_sir(unsigned int sir) @@ -774,32 +682,20 @@ static inline void cp15_pmu_sir(unsigned int sir) static inline void cp15_pmu_wrecsr(unsigned int ecsr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c12, 5\n" - : - : "r" (ecsr) - : "memory" - ); + CP15_SET(PMSELR, ecsr); } /**************************************************************************** * Name: cp15_pmu_wretsr * * Description: - * Write the Performance Monitors Event Type Select Register (PMETSR) + * Write the Performance Monitors Event Type Select Register (PMXEVTYPER) * ****************************************************************************/ static inline void cp15_pmu_wretsr(unsigned int etsr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c13, 1\n" - : - : "r" (etsr) - : "memory" - ); + CP15_SET(PMXEVTYPER, etsr); } /**************************************************************************** @@ -812,27 +708,12 @@ static inline void cp15_pmu_wretsr(unsigned int etsr) static inline unsigned int cp15_pmu_rduer(void) { - unsigned int uer; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c14, 0\n" - : "=r" (uer) - : - : "memory" - ); - - return uer; + return CP15_GET(PMUSERENR); } static inline void cp15_pmu_wruer(unsigned int uer) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c14, 0\n" - : - : "r" (uer) - : "memory" - ); + CP15_SET(PMUSERENR, uer); } static inline void cp15_pmu_uer(unsigned int uer) @@ -851,13 +732,7 @@ static inline void cp15_pmu_uer(unsigned int uer) static inline void cp15_pmu_wriesr(unsigned int iesr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c14, 1\n" - : - : "r" (iesr) - : "memory" - ); + CP15_SET(PMINTENSET, iesr); } /**************************************************************************** @@ -871,13 +746,7 @@ static inline void cp15_pmu_wriesr(unsigned int iesr) static inline void cp15_pmu_wriecr(unsigned int iecr) { - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c9, c14, 2\n" - : - : "r" (iecr) - : "memory" - ); + CP15_SET(PMINTENCLR, iecr); } /**************************************************************************** @@ -890,16 +759,7 @@ static inline void cp15_pmu_wriecr(unsigned int iecr) static inline unsigned int cp15_pmu_rdccr(void) { - unsigned int ccr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c13, 0\n" - : "=r" (ccr) - : - : "memory" - ); - - return ccr; + return CP15_GET(PMCCNTR); } /**************************************************************************** @@ -912,16 +772,7 @@ static inline unsigned int cp15_pmu_rdccr(void) static inline unsigned int cp15_pmu_rdecr(void) { - unsigned int ecr; - __asm__ __volatile__ - ( - "\tmrc p15, 0, %0, c9, c13, 2" - : "=r" (ecr) - : - : "memory" - ); - - return ecr; + return CP15_GET(PMXEVCNTR); } #endif /* __ASSEMBLY__ */
