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commit 4abd6262883c632deca2a5059a3fd565cdeb4211 Author: Xiang Xiao <[email protected]> AuthorDate: Sat Nov 19 04:14:45 2022 +0800 arch/armv7-r: Remove the nonexistent SCTLR_IE Signed-off-by: Xiang Xiao <[email protected]> --- arch/arm/src/armv7-r/arm_head.S | 3 +-- arch/arm/src/armv7-r/sctlr.h | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index 8d163a0ed0..d367533e46 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -191,7 +191,6 @@ __start: * SCTLR_EE Bit 25: 0=Little endian. * SCTLR_NMFI Bit 27: Non-maskable FIQ (NMFI) support * SCTLR_TE Bit 30: All exceptions handled in ARM state. - * SCTLR_IE Bit 31: Instruction endian-ness. */ /* Clear all configurable bits */ @@ -199,7 +198,7 @@ __start: bic r0, r0, #(SCTLR_M | SCTLR_A | SCTLR_C | SCTLR_CCP15BEN | SCTLR_B) bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR) bic r0, r0, #(SCTLR_BR | SCTLR_DZ | SCTLR_FI | SCTLR_U) - bic r0, r0, #(SCTLR_VE | SCTLR_EE | SCTLR_NMFI | SCTLR_TE | SCTLR_IE) + bic r0, r0, #(SCTLR_VE | SCTLR_EE | SCTLR_NMFI | SCTLR_TE) /* Set configured bits */ diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h index 78c589e03c..532cc3617c 100644 --- a/arch/arm/src/armv7-r/sctlr.h +++ b/arch/arm/src/armv7-r/sctlr.h @@ -159,7 +159,6 @@ #define SCTLR_NMFI (1 << 27) /* Bit 27: Non-maskable FIQ (NMFI) support */ /* Bits 28-29: Reserved */ #define SCTLR_TE (1 << 30) /* Bit 30: Thumb exception enable */ -#define SCTLR_IE (1 << 31) /* Bit 31: Instruction endian-ness */ /* Auxiliary Control Register (ACTLR): CRn=c1, opc1=0, CRm=c0, opc2=1 * Implementation defined
