pkarashchenko commented on code in PR #9024: URL: https://github.com/apache/nuttx/pull/9024#discussion_r1176779443
########## arch/arm/src/imxrt/hardware/imxrt_flexio.h: ########## @@ -0,0 +1,743 @@ +/**************************************************************************** + * arch/arm/src/imxrt/hardware/imxrt_flexio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXIO_H +#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include "hardware/imxrt_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMXRT_FLEXIO_VERID_OFFSET 0x0000 /* Version ID Register, offset: 0x0 */ +#define IMXRT_FLEXIO_PARAM_OFFSET 0x0004 /* Parameter Register, offset: 0x4 */ +#define IMXRT_FLEXIO_CTRL_OFFSET 0x0008 /* FlexIO Control Register, offset: 0x8 */ +#define IMXRT_FLEXIO_PIN_OFFSET 0x000c /* Pin State Register, offset: 0xC */ +#define IMXRT_FLEXIO_SHIFTSTAT_OFFSET 0x0010 /* Shifter Status Register, offset: 0x10 */ +#define IMXRT_FLEXIO_SHIFTERR_OFFSET 0x0014 /* Shifter Error Register, offset: 0x14 */ +#define IMXRT_FLEXIO_TIMSTAT_OFFSET 0x0018 /* Timer Status Register, offset: 0x18 */ +#define IMXRT_FLEXIO_SHIFTSIEN_OFFSET 0x0020 /* Shift Enable, offset: 0x20 */ +#define IMXRT_FLEXIO_SHIFTEIEN_OFFSET 0x0024 /* Shifter Error Interrupt Enable, offset: 0x24 */ +#define IMXRT_FLEXIO_TIMIEN_OFFSET 0x0028 /* Timer Interrupt Enable Register, offset: 0x28 */ +#define IMXRT_FLEXIO_SHIFTSDEN_OFFSET 0x0030 /* Shifter Status DMA Enable, offset: 0x30 */ +#define IMXRT_FLEXIO_SHIFTSTATE_OFFSET 0x0040 /* Shifter State Register, offset: 0x40 */ +#define IMXRT_FLEXIO_SHIFTCTL0_OFFSET 0x0080 /* Shifter Control N Register, array offset: 0x80, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTCTL1_OFFSET 0x0084 +#define IMXRT_FLEXIO_SHIFTCTL2_OFFSET 0x0088 +#define IMXRT_FLEXIO_SHIFTCTL3_OFFSET 0x008c +#define IMXRT_FLEXIO_SHIFTCTL4_OFFSET 0x0090 +#define IMXRT_FLEXIO_SHIFTCTL5_OFFSET 0x0094 +#define IMXRT_FLEXIO_SHIFTCTL6_OFFSET 0x0098 +#define IMXRT_FLEXIO_SHIFTCTL7_OFFSET 0x009c +#define IMXRT_FLEXIO_SHIFTCFG0_OFFSET 0x0100 /* Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTCFG1_OFFSET 0x0104 +#define IMXRT_FLEXIO_SHIFTCFG2_OFFSET 0x0108 +#define IMXRT_FLEXIO_SHIFTCFG3_OFFSET 0x010c +#define IMXRT_FLEXIO_SHIFTCFG4_OFFSET 0x0110 +#define IMXRT_FLEXIO_SHIFTCFG5_OFFSET 0x0114 +#define IMXRT_FLEXIO_SHIFTCFG6_OFFSET 0x0118 +#define IMXRT_FLEXIO_SHIFTCFG7_OFFSET 0x011c +#define IMXRT_FLEXIO_SHIFTBUF0_OFFSET 0x0200 /* Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTBUF1_OFFSET 0x0204 +#define IMXRT_FLEXIO_SHIFTBUF2_OFFSET 0x0208 +#define IMXRT_FLEXIO_SHIFTBUF3_OFFSET 0x020c +#define IMXRT_FLEXIO_SHIFTBUF4_OFFSET 0x0210 +#define IMXRT_FLEXIO_SHIFTBUF5_OFFSET 0x0214 +#define IMXRT_FLEXIO_SHIFTBUF6_OFFSET 0x0218 +#define IMXRT_FLEXIO_SHIFTBUF7_OFFSET 0x021c +#define IMXRT_FLEXIO_SHIFTBUFBIS0_OFFSET 0x0280 /* Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTBUFBIS1_OFFSET 0x0284 +#define IMXRT_FLEXIO_SHIFTBUFBIS2_OFFSET 0x0288 +#define IMXRT_FLEXIO_SHIFTBUFBIS3_OFFSET 0x028c +#define IMXRT_FLEXIO_SHIFTBUFBIS4_OFFSET 0x0290 +#define IMXRT_FLEXIO_SHIFTBUFBIS5_OFFSET 0x0294 +#define IMXRT_FLEXIO_SHIFTBUFBIS6_OFFSET 0x0298 +#define IMXRT_FLEXIO_SHIFTBUFBIS7_OFFSET 0x029c +#define IMXRT_FLEXIO_SHIFTBUFBYS0_OFFSET 0x0300 /* Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTBUFBYS1_OFFSET 0x0304 +#define IMXRT_FLEXIO_SHIFTBUFBYS2_OFFSET 0x0308 +#define IMXRT_FLEXIO_SHIFTBUFBYS3_OFFSET 0x030c +#define IMXRT_FLEXIO_SHIFTBUFBYS4_OFFSET 0x0310 +#define IMXRT_FLEXIO_SHIFTBUFBYS5_OFFSET 0x0314 +#define IMXRT_FLEXIO_SHIFTBUFBYS6_OFFSET 0x0318 +#define IMXRT_FLEXIO_SHIFTBUFBYS7_OFFSET 0x031c +#define IMXRT_FLEXIO_SHIFTBUFBBS0_OFFSET 0x0380 /* Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTBUFBBS1_OFFSET 0x0384 +#define IMXRT_FLEXIO_SHIFTBUFBBS2_OFFSET 0x0388 +#define IMXRT_FLEXIO_SHIFTBUFBBS3_OFFSET 0x038c +#define IMXRT_FLEXIO_SHIFTBUFBBS4_OFFSET 0x0390 +#define IMXRT_FLEXIO_SHIFTBUFBBS5_OFFSET 0x0394 +#define IMXRT_FLEXIO_SHIFTBUFBBS6_OFFSET 0x0398 +#define IMXRT_FLEXIO_SHIFTBUFBBS7_OFFSET 0x039c +#define IMXRT_FLEXIO_TIMCTL0_OFFSET 0x0400 /* Timer Control N Register, array offset: 0x400, array step: 0x4 */ +#define IMXRT_FLEXIO_TIMCTL1_OFFSET 0x0404 +#define IMXRT_FLEXIO_TIMCTL2_OFFSET 0x0408 +#define IMXRT_FLEXIO_TIMCTL3_OFFSET 0x040c +#define IMXRT_FLEXIO_TIMCTL4_OFFSET 0x0410 +#define IMXRT_FLEXIO_TIMCTL5_OFFSET 0x0414 +#define IMXRT_FLEXIO_TIMCTL6_OFFSET 0x0418 +#define IMXRT_FLEXIO_TIMCTL7_OFFSET 0x041c +#define IMXRT_FLEXIO_TIMCFG0_OFFSET 0x0480 /* Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ +#define IMXRT_FLEXIO_TIMCFG1_OFFSET 0x0484 +#define IMXRT_FLEXIO_TIMCFG2_OFFSET 0x0488 +#define IMXRT_FLEXIO_TIMCFG3_OFFSET 0x048c +#define IMXRT_FLEXIO_TIMCFG4_OFFSET 0x0490 +#define IMXRT_FLEXIO_TIMCFG5_OFFSET 0x0494 +#define IMXRT_FLEXIO_TIMCFG6_OFFSET 0x0498 +#define IMXRT_FLEXIO_TIMCFG7_OFFSET 0x049c +#define IMXRT_FLEXIO_TIMCMP0_OFFSET 0x0500 /* Timer Compare N Register, array offset: 0x500, array step: 0x4 */ +#define IMXRT_FLEXIO_TIMCMP1_OFFSET 0x0504 +#define IMXRT_FLEXIO_TIMCMP2_OFFSET 0x0508 +#define IMXRT_FLEXIO_TIMCMP3_OFFSET 0x050c +#define IMXRT_FLEXIO_TIMCMP4_OFFSET 0x0510 +#define IMXRT_FLEXIO_TIMCMP5_OFFSET 0x0514 +#define IMXRT_FLEXIO_TIMCMP6_OFFSET 0x0518 +#define IMXRT_FLEXIO_TIMCMP7_OFFSET 0x051c +#define IMXRT_FLEXIO_SHIFTBUFNBS0_OFFSET 0x0680 /* Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTBUFNBS1_OFFSET 0x0684 +#define IMXRT_FLEXIO_SHIFTBUFNBS2_OFFSET 0x0688 +#define IMXRT_FLEXIO_SHIFTBUFNBS3_OFFSET 0x068c +#define IMXRT_FLEXIO_SHIFTBUFNBS4_OFFSET 0x0690 +#define IMXRT_FLEXIO_SHIFTBUFNBS5_OFFSET 0x0694 +#define IMXRT_FLEXIO_SHIFTBUFNBS6_OFFSET 0x0698 +#define IMXRT_FLEXIO_SHIFTBUFNBS7_OFFSET 0x069c +#define IMXRT_FLEXIO_SHIFTBUFHWS0_OFFSET 0x0700 /* Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTBUFHWS1_OFFSET 0x0704 +#define IMXRT_FLEXIO_SHIFTBUFHWS2_OFFSET 0x0708 +#define IMXRT_FLEXIO_SHIFTBUFHWS3_OFFSET 0x070c +#define IMXRT_FLEXIO_SHIFTBUFHWS4_OFFSET 0x0710 +#define IMXRT_FLEXIO_SHIFTBUFHWS5_OFFSET 0x0714 +#define IMXRT_FLEXIO_SHIFTBUFHWS6_OFFSET 0x0718 +#define IMXRT_FLEXIO_SHIFTBUFHWS7_OFFSET 0x071c +#define IMXRT_FLEXIO_SHIFTBUFNIS0_OFFSET 0x0780 /* Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ +#define IMXRT_FLEXIO_SHIFTBUFNIS1_OFFSET 0x0784 +#define IMXRT_FLEXIO_SHIFTBUFNIS2_OFFSET 0x0788 +#define IMXRT_FLEXIO_SHIFTBUFNIS3_OFFSET 0x078c +#define IMXRT_FLEXIO_SHIFTBUFNIS4_OFFSET 0x0790 +#define IMXRT_FLEXIO_SHIFTBUFNIS5_OFFSET 0x0794 +#define IMXRT_FLEXIO_SHIFTBUFNIS6_OFFSET 0x0798 +#define IMXRT_FLEXIO_SHIFTBUFNIS7_OFFSET 0x079c + +/* VERID - Version ID Register */ + +#define FLEXIO_VERID_FEATURE_MASK (0xffffu) +#define FLEXIO_VERID_FEATURE_SHIFT (0u) + +/* FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented. + * 0b0000000000000001..Supports state, logic and parallel modes. + */ + +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xff0000u) +#define FLEXIO_VERID_MINOR_SHIFT (16u) + +/* MINOR - Minor Version Number */ + +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xff000000u) +#define FLEXIO_VERID_MAJOR_SHIFT (24u) + +/* MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) Review Comment: I think that outer cast can be omitted -- This is an automated message from the Apache Git Service. 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