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commit 26536f9f5552483bd44555335ce36be59bb690bc Author: raiden00pl <[email protected]> AuthorDate: Wed May 10 20:45:11 2023 +0200 boards/stm32f7: rework boards to not use CONFIG_STM32F7_USE_LEGACY_PINMAP=y In reference to PR #8992 --- .../stm32f7/nucleo-144/configs/f722-can/defconfig | 1 + .../nucleo-144/configs/f722-cansock/defconfig | 1 + .../nucleo-144/configs/f722-composite/defconfig | 1 + .../stm32f7/nucleo-144/configs/f722-nsh/defconfig | 1 + .../nucleo-144/configs/f746-evalos/defconfig | 1 + .../stm32f7/nucleo-144/configs/f746-nsh/defconfig | 1 + .../nucleo-144/configs/f746-pysim/defconfig | 1 + .../nucleo-144/configs/f767-evalos/defconfig | 1 + .../nucleo-144/configs/f767-netnsh/defconfig | 1 + .../stm32f7/nucleo-144/configs/f767-nsh/defconfig | 1 + boards/arm/stm32f7/nucleo-144/include/board.h | 168 ++++++----- .../steval-eth001v1/configs/foc_b16/defconfig | 1 + .../steval-eth001v1/configs/foc_f32/defconfig | 1 + .../stm32f7/steval-eth001v1/configs/nsh/defconfig | 1 + boards/arm/stm32f7/steval-eth001v1/include/board.h | 51 +++- .../arm/stm32f7/stm32f746-ws/configs/nsh/defconfig | 1 + boards/arm/stm32f7/stm32f746-ws/include/board.h | 116 +++++--- .../stm32f746g-disco/configs/audio/defconfig | 1 + .../stm32f7/stm32f746g-disco/configs/fb/defconfig | 1 + .../stm32f746g-disco/configs/lvgl/defconfig | 1 + .../stm32f746g-disco/configs/netnsh/defconfig | 1 + .../stm32f7/stm32f746g-disco/configs/nsh/defconfig | 1 + .../stm32f746g-disco/configs/nxdemo/defconfig | 1 + .../stm32f746g-disco/configs/nxterm/defconfig | 1 + .../arm/stm32f7/stm32f746g-disco/include/board.h | 329 ++++++++++++--------- .../stm32f769i-disco/configs/netnsh/defconfig | 1 + .../stm32f7/stm32f769i-disco/configs/nsh/defconfig | 1 + .../arm/stm32f7/stm32f769i-disco/include/board.h | 166 ++++++----- .../stm32f777zit6-meadow/configs/nsh/defconfig | 1 + .../stm32f7/stm32f777zit6-meadow/include/board.h | 173 ++++++----- 30 files changed, 608 insertions(+), 419 deletions(-) diff --git a/boards/arm/stm32f7/nucleo-144/configs/f722-can/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f722-can/defconfig index 5f35d2cda5..f51b1bfb30 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f722-can/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f722-can/defconfig @@ -6,6 +6,7 @@ # modifications. # # CONFIG_ARCH_FPU is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f722-cansock/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f722-cansock/defconfig index 0df46ea98b..add1bfa7d4 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f722-cansock/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f722-cansock/defconfig @@ -8,6 +8,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NET_ETHERNET is not set # CONFIG_NET_IPv4 is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f722-composite/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f722-composite/defconfig index 3bd41ccb58..43d010d350 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f722-composite/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f722-composite/defconfig @@ -6,6 +6,7 @@ # modifications. # # CONFIG_ARCH_FPU is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig index de53378df3..e85573bff8 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f722-nsh/defconfig @@ -8,6 +8,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig index 197f3d2527..c6e3abe086 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-evalos/defconfig @@ -10,6 +10,7 @@ # CONFIG_DISABLE_OS_API is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig index 68d1e77729..f4144cba97 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-nsh/defconfig @@ -8,6 +8,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig index ec3a272265..dcdff4bc6f 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f746-pysim/defconfig @@ -7,6 +7,7 @@ # # CONFIG_NDEBUG is not set # CONFIG_STM32F7_DTCMEXCLUDE is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ADC=y CONFIG_ADC_FIFOSIZE=16 CONFIG_ANALOG=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig index 22bc1d77dc..13bcd7ed1c 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-evalos/defconfig @@ -10,6 +10,7 @@ # CONFIG_DISABLE_OS_API is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig index 860eed9221..ecd4b61608 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-netnsh/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig b/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig index 7b6c87e7fa..a79a777388 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-144/configs/f767-nsh/defconfig @@ -8,6 +8,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-144" CONFIG_ARCH_BOARD_NUCLEO_144=y diff --git a/boards/arm/stm32f7/nucleo-144/include/board.h b/boards/arm/stm32f7/nucleo-144/include/board.h index 2b5ea54ed3..81212b3083 100644 --- a/boards/arm/stm32f7/nucleo-144/include/board.h +++ b/boards/arm/stm32f7/nucleo-144/include/board.h @@ -221,13 +221,6 @@ # define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif -#if defined(CONFIG_STM32F7_SDMMC2) -# define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_1 -# define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_1 -# define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1 -# define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1 -#endif - /* DMA Channel/Stream Selections ********************************************/ /* Stream selections are arbitrary for now but might become important in the @@ -326,43 +319,67 @@ #define NUM_BUTTONS 1 #define BUTTON_USER_BIT (1 << BUTTON_USER) +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 +#define ADC2_DMA_CHAN DMAMAP_ADC2_1 +#define ADC3_DMA_CHAN DMAMAP_ADC3_1 + /* Alternate function pin selections ****************************************/ +/* ADC1 */ + +#define GPIO_ADC1_IN0 GPIO_ADC1_IN0_0 /* PA0 */ +#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA1 */ +#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA2 */ +#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA3 */ +#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA4 */ +#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PA5 */ +#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 /* PA6 */ +#define GPIO_ADC1_IN7 GPIO_ADC1_IN7_0 /* PA7 */ +#define GPIO_ADC1_IN8 GPIO_ADC1_IN8_0 /* PB0 */ +#define GPIO_ADC1_IN9 GPIO_ADC1_IN9_0 /* PB1 */ +#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PC0 */ +#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PC1 */ +#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PC2 */ +#define GPIO_ADC1_IN13 GPIO_ADC1_IN13_0 /* PC3 */ +#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PC4 */ +#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PC5 */ + /* TIM */ /* Quadrature encoder * Default is to use timer 8 (16-bit) and encoder on PC6/PC7 * We use here TIM2 with a 32-bit counter on PA15/PB3 */ -#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_2 -#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_2 -#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_2 -#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_2 +#define GPIO_TIM1_CH1IN (GPIO_TIM1_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM1_CH2IN (GPIO_TIM1_CH2IN_2|GPIO_SPEED_50MHz) + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_2 -#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_2 +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM4_CH1IN GPIO_TIM4_CH1IN_2 -#define GPIO_TIM4_CH2IN GPIO_TIM4_CH2IN_2 +#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2|GPIO_SPEED_50MHz) /* PWM * Use Timer 1 or 3 */ -#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_2 -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT -#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1NOUT_3 -#endif -#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_2 -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT -#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2NOUT_3 -#endif +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_3|GPIO_SPEED_50MHz) +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_3|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_2 -#define GPIO_TIM3_CH2OUT GPIO_TIM3_CH2OUT_2 -#define GPIO_TIM3_CH3OUT GPIO_TIM3_CH3OUT_2 -#define GPIO_TIM3_CH4OUT GPIO_TIM3_CH4OUT_1 +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_50MHz) #if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO) @@ -380,8 +397,8 @@ * -- ----- --------- ----- */ - # define GPIO_USART6_RX GPIO_USART6_RX_2 - # define GPIO_USART6_TX GPIO_USART6_TX_2 +# define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) +# define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) #endif /* USART3: @@ -389,8 +406,8 @@ */ #if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL) - # define GPIO_USART3_RX GPIO_USART3_RX_3 - # define GPIO_USART3_TX GPIO_USART3_TX_3 +# define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) +# define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) #endif #if defined(CONFIG_NUCLEO_CONSOLE_MORPHO_UART4) @@ -409,18 +426,18 @@ * ------- --------- ----- */ -# define GPIO_UART4_RX GPIO_UART4_RX_1 -# define GPIO_UART4_TX GPIO_UART4_TX_1 +# define GPIO_UART4_RX (GPIO_UART4_RX_1|GPIO_SPEED_100MHz) +# define GPIO_UART4_TX (GPIO_UART4_TX_1|GPIO_SPEED_100MHz) /* USART3 seems to be forced selected by the Nucleo-F746ZG kconfig - bug */ -# define GPIO_USART3_RX GPIO_USART3_RX_1 -# define GPIO_USART3_TX GPIO_USART3_TX_1 +# define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) +# define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* USART6 seems to be forced selected by the Nucleo-F722E kconfig - bug */ -# define GPIO_USART6_RX GPIO_USART6_RX_2 -# define GPIO_USART6_TX GPIO_USART6_TX_2 +# define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) +# define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) #endif @@ -433,14 +450,6 @@ * USART8: has no remap */ -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 -#define ADC2_DMA_CHAN DMAMAP_ADC2_1 -#define ADC3_DMA_CHAN DMAMAP_ADC3_1 - /* SPI * * @@ -457,17 +466,17 @@ * PB3 SPI3_SCK CN12-31 */ -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 -#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 -#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3 +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 -#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2 -#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) /* I2C * @@ -483,14 +492,14 @@ * */ -#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 -#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 -#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1 -#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1 +#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) /* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins: * @@ -514,18 +523,43 @@ * PG2 is not controlled but appears to result in a PHY address of 0. */ -#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2 -#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 -#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1 +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) /* CAN Bus */ #ifdef CONFIG_NUCLEO_CAN1_MAP_PD0PD1 -# define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */ -# define GPIO_CAN1_RX GPIO_CAN1_RX_3 /* PD0 */ +# define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) /* PD1 */ +# define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) /* PD0 */ #elif CONFIG_NUCLEO_144_CAN1_MAP_D14D15 -# define GPIO_CAN1_TX GPIO_CAN1_TX_2 /* PB9 */ -# define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */ +# define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ +# define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ #endif +/* SDMMC2 */ + +#define GPIO_SDMMC2_CK (GPIO_SDMMC2_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_CMD (GPIO_SDMMC2_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D0 (GPIO_SDMMC2_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D1 (GPIO_SDMMC2_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D4 (GPIO_SDMMC2_D4_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D5 (GPIO_SDMMC2_D5_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D6 (GPIO_SDMMC2_D6_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D7 (GPIO_SDMMC2_D7_0|GPIO_SPEED_50MHz) + +/* OTGFS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) + #endif /* __BOARDS_ARM_STM32F7_NUCLEO_144_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig index 574e4d52dd..b86a9515c2 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig @@ -8,6 +8,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ADC=y CONFIG_ADC_FIFOSIZE=2 CONFIG_ANALOG=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig index 204e904b43..4564385dc7 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig @@ -8,6 +8,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ADC=y CONFIG_ADC_FIFOSIZE=2 CONFIG_ANALOG=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig index be3772af5f..30ddaade19 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig @@ -8,6 +8,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y diff --git a/boards/arm/stm32f7/steval-eth001v1/include/board.h b/boards/arm/stm32f7/steval-eth001v1/include/board.h index b8a0c3d8a7..8062dcfb37 100644 --- a/boards/arm/stm32f7/steval-eth001v1/include/board.h +++ b/boards/arm/stm32f7/steval-eth001v1/include/board.h @@ -184,13 +184,32 @@ /* Alternate function pin selections ****************************************/ +/* ADC1 */ + +#define GPIO_ADC1_IN0 GPIO_ADC1_IN0_0 /* PA0 */ +#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA1 */ +#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA2 */ +#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA3 */ +#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA4 */ +#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PA5 */ +#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 /* PA6 */ +#define GPIO_ADC1_IN7 GPIO_ADC1_IN7_0 /* PA7 */ +#define GPIO_ADC1_IN8 GPIO_ADC1_IN8_0 /* PB0 */ +#define GPIO_ADC1_IN9 GPIO_ADC1_IN9_0 /* PB1 */ +#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PC0 */ +#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PC1 */ +#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PC2 */ +#define GPIO_ADC1_IN13 GPIO_ADC1_IN13_0 /* PC3 */ +#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PC4 */ +#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PC5 */ + /* USART3 * TX - PB10 * RX - PB11 */ -#define GPIO_USART3_RX GPIO_USART3_RX_1 /* PB11 */ -#define GPIO_USART3_TX GPIO_USART3_TX_1 /* PB10 */ +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ /* USART6 (RS485) * TX - PG14 @@ -199,25 +218,25 @@ * CK - PC8 */ -#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */ -#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */ -#define GPIO_USART6_RTS GPIO_USART6_RTS_1 /* PG12 */ -#define GPIO_USART6_CK GPIO_USART6_CK_1 /* PC8 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) /* PG14 */ +#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) /* PG9 */ +#define GPIO_USART6_RTS GPIO_USART6_RTS_1 /* PG12 */ +#define GPIO_USART6_CK GPIO_USART6_CK_1 /* PC8 */ /* PWM1 - FOC */ -#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 /* PA8 */ -#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1NOUT_2 /* PB13 */ -#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_1 /* PA9 */ -#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2NOUT_1 /* PB0 */ -#define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_1 /* PA10 */ -#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3NOUT_1 /* PB1 */ -#define GPIO_TIM1_CH4OUT 0 /* not used as output */ +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_2|GPIO_SPEED_50MHz) /* PB13 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* PA9 */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1|GPIO_SPEED_50MHz) /* PB0 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* PA10 */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_1|GPIO_SPEED_50MHz) /* PB1 */ +#define GPIO_TIM1_CH4OUT 0 /* not used as output */ /* TIM2 - QENCO */ -#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_1 /* PA0 */ -#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1 /* PA1 */ -#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_1 /* PA2 */ +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1|GPIO_SPEED_50MHz) /* PA0 */ +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) /* PA1 */ +#define GPIO_TIM2_CH3IN (GPIO_TIM2_CH3IN_1|GPIO_SPEED_50MHz) /* PA2 */ #endif /* __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig index 82bf3b39eb..491ad8e1bd 100644 --- a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig @@ -9,6 +9,7 @@ # CONFIG_MMCSD_SPI is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ADC=y CONFIG_ANALOG=y CONFIG_ARCH="arm" diff --git a/boards/arm/stm32f7/stm32f746-ws/include/board.h b/boards/arm/stm32f7/stm32f746-ws/include/board.h index b6643718dc..47edc212fb 100644 --- a/boards/arm/stm32f7/stm32f746-ws/include/board.h +++ b/boards/arm/stm32f7/stm32f746-ws/include/board.h @@ -206,44 +206,6 @@ #define BOARD_FLASH_WAITSTATES 7 -/* Alternate function pin selections ****************************************/ - -/* USART6: - * - * These configurations assume that you are using a standard Arduio RS-232 - * shield with the serial interface with RX on pin D0 and TX on pin D1: - * - * -------- --------------- - * STM32F7 - * ARDUIONO FUNCTION GPIO - * -- ----- --------- ----- - * DO RX USART6_RX PC7 - * D1 TX USART6_TX PC6 - * -- ----- --------- ----- - */ - -#define GPIO_USART6_RX GPIO_USART6_RX_1 -#define GPIO_USART6_TX GPIO_USART6_TX_1 - -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 - -#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 -#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 - -/* SDMMC */ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 - * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 - /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses * to service FIFOs in interrupt driven mode. These values have not been @@ -274,4 +236,82 @@ # define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif +/* DMA channels *************************************************************/ + +/* SDMMC */ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 + * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 + +/* Alternate function pin selections ****************************************/ + +/* ADC1 */ + +#define GPIO_ADC1_IN0 GPIO_ADC1_IN0_0 /* PA0 */ +#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA1 */ +#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA2 */ +#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA3 */ +#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA4 */ +#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PA5 */ +#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 /* PA6 */ +#define GPIO_ADC1_IN7 GPIO_ADC1_IN7_0 /* PA7 */ +#define GPIO_ADC1_IN8 GPIO_ADC1_IN8_0 /* PB0 */ +#define GPIO_ADC1_IN9 GPIO_ADC1_IN9_0 /* PB1 */ +#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PC0 */ +#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PC1 */ +#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PC2 */ +#define GPIO_ADC1_IN13 GPIO_ADC1_IN13_0 /* PC3 */ +#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PC4 */ +#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PC5 */ + +/* USART6: + * + * These configurations assume that you are using a standard Arduio RS-232 + * shield with the serial interface with RX on pin D0 and TX on pin D1: + * + * -------- --------------- + * STM32F7 + * ARDUIONO FUNCTION GPIO + * -- ----- --------- ----- + * DO RX USART6_RX PC7 + * D1 TX USART6_TX PC6 + * -- ----- --------- ----- + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) + +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) + +/* SDMMC1 */ + +#define GPIO_SDMMC1_CK (GPIO_SDMMC1_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_CMD (GPIO_SDMMC1_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D0 (GPIO_SDMMC1_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D1 (GPIO_SDMMC1_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D2 (GPIO_SDMMC1_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D3 (GPIO_SDMMC1_D3_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D4 (GPIO_SDMMC1_D4_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D5 (GPIO_SDMMC1_D5_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D6 (GPIO_SDMMC1_D6_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D7 (GPIO_SDMMC1_D7_0|GPIO_SPEED_50MHz) + +/* OTGFS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) + #endif /* __BOARDS_ARM_STM32F7_STM32F746_WS_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig index c7b897a8a9..35c785db5f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig @@ -7,6 +7,7 @@ # # CONFIG_ARCH_FPU is not set # CONFIG_SPI_CALLBACK is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig index 2578dc05ff..fc7e8f3fe8 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig @@ -10,6 +10,7 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STM32F7_FB_CMAP is not set # CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig index 77d32940f9..dcf4cae4f6 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig @@ -11,6 +11,7 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STM32F7_FB_CMAP is not set # CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig index 1c1d102423..f1f8dc68af 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig @@ -6,6 +6,7 @@ # modifications. # # CONFIG_ARCH_FPU is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig index bf50f1d7ea..b48faa0f2e 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig @@ -8,6 +8,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig index 3e5a69b2bf..dd2c302501 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig @@ -11,6 +11,7 @@ # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_STM32F7_FB_CMAP is not set # CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig index de69cd8428..92e793f1da 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig @@ -12,6 +12,7 @@ # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_STM32F7_FB_CMAP is not set # CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index 409ad5650a..d06ce9c647 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -247,7 +247,39 @@ #define BOARD_FLASH_WAITSTATES 7 -/* LED definitions */ +/* SDMMC */ + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ /* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located * near the reset button, that can be controlled by software (LD2 is a power @@ -303,7 +335,7 @@ #define LED_ASSERTION 2 /* LD1=no change */ #define LED_PANIC 3 /* LD1=flashing */ -/* Button definitions */ +/* Button definitions *******************************************************/ /* The STM32F7 Discovery supports one button: * Pushbutton B1, labelled "User", is connected to GPIO PI11. @@ -314,7 +346,55 @@ #define NUM_BUTTONS 1 #define BUTTON_USER_BIT (1 << BUTTON_USER) -/* Alternate function pin selections */ +/* LCD definitions **********************************************************/ + +#define BOARD_LTDC_WIDTH 480 +#define BOARD_LTDC_HEIGHT 272 + +#define BOARD_LTDC_OUTPUT_BPP 24 +#define BOARD_LTDC_HFP 32 +#define BOARD_LTDC_HBP 13 +#define BOARD_LTDC_VFP 2 +#define BOARD_LTDC_VBP 2 +#define BOARD_LTDC_HSYNC 41 +#define BOARD_LTDC_VSYNC 10 + +#define BOARD_LTDC_PLLSAIN 192 +#define BOARD_LTDC_PLLSAIR 5 + +/* Pixel Clock Polarity */ + +#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ + +/* Data Enable Polarity */ + +#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ + +/* Vertical Sync Polarity */ + +#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ + +/* Horizontal Sync Polarity */ + +#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ + +/* DMA channels *************************************************************/ + +#define DMACHAN_SAI2_A DMAMAP_SAI2_A +#define DMACHAN_SAI2_B DMAMAP_SAI2_B +#define DMACHAN_SAI1_B DMAMAP_SAI1_B + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 + * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 + +/* Alternate function pin selections ****************************************/ /* USART6: * @@ -330,8 +410,8 @@ * -- ----- --------- ----- */ -#define GPIO_USART6_RX GPIO_USART6_RX_1 -#define GPIO_USART6_TX GPIO_USART6_TX_1 +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* USART1: * @@ -347,15 +427,15 @@ * -- ----- --------- ----- */ -#define GPIO_USART1_RX GPIO_USART1_RX_2 -#define GPIO_USART1_TX GPIO_USART1_TX_1 +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* I2C1 - the I2C1 bus is shared by audio (Cirrus WM8994), * camera (DCMI SDA/SCL) and external connectors CN2 & Arduino D14/D15. */ -#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 -#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) /* I2C - There is a FT5336 TouchPanel on I2C3 using these pins: */ @@ -389,144 +469,109 @@ * PG2 is not controlled but appears to result in a PHY address of 0. */ -#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2 -#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 -#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2 - -/* LCD definitions */ - -#define BOARD_LTDC_WIDTH 480 -#define BOARD_LTDC_HEIGHT 272 - -#define BOARD_LTDC_OUTPUT_BPP 24 -#define BOARD_LTDC_HFP 32 -#define BOARD_LTDC_HBP 13 -#define BOARD_LTDC_VFP 2 -#define BOARD_LTDC_VBP 2 -#define BOARD_LTDC_HSYNC 41 -#define BOARD_LTDC_VSYNC 10 - -#define BOARD_LTDC_PLLSAIN 192 -#define BOARD_LTDC_PLLSAIR 5 - -/* Pixel Clock Polarity */ - -#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ - -/* Data Enable Polarity */ - -#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ - -/* Vertical Sync Polarity */ - -#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ - -/* Horizontal Sync Polarity */ - -#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ - -/* GPIO pinset */ - -#define GPIO_LTDC_PINS 24 /* 24-bit display */ - -#define GPIO_LTDC_R0 GPIO_LTDC_R0_3 -#define GPIO_LTDC_R1 GPIO_LTDC_R1_3 -#define GPIO_LTDC_R2 GPIO_LTDC_R2_4 -#define GPIO_LTDC_R3 GPIO_LTDC_R3_3 -#define GPIO_LTDC_R4 GPIO_LTDC_R4_4 -#define GPIO_LTDC_R5 GPIO_LTDC_R5_4 -#define GPIO_LTDC_R6 GPIO_LTDC_R6_4 -#define GPIO_LTDC_R7 GPIO_LTDC_R7_3 - -#define GPIO_LTDC_G0 GPIO_LTDC_G0_2 -#define GPIO_LTDC_G1 GPIO_LTDC_G1_2 -#define GPIO_LTDC_G2 GPIO_LTDC_G2_3 -#define GPIO_LTDC_G3 GPIO_LTDC_G3_4 -#define GPIO_LTDC_G4 GPIO_LTDC_G4_3 -#define GPIO_LTDC_G5 GPIO_LTDC_G5_3 -#define GPIO_LTDC_G6 GPIO_LTDC_G6_3 -#define GPIO_LTDC_G7 GPIO_LTDC_G7_3 - -#define GPIO_LTDC_B0 GPIO_LTDC_B0_1 -#define GPIO_LTDC_B1 GPIO_LTDC_B1_2 -#define GPIO_LTDC_B2 GPIO_LTDC_B2_3 -#define GPIO_LTDC_B3 GPIO_LTDC_B3_3 -#define GPIO_LTDC_B4 GPIO_LTDC_B4_4 -#define GPIO_LTDC_B5 GPIO_LTDC_B5_3 -#define GPIO_LTDC_B6 GPIO_LTDC_B6_3 -#define GPIO_LTDC_B7 GPIO_LTDC_B7_3 - -#define GPIO_LTDC_VSYNC GPIO_LTDC_VSYNC_2 -#define GPIO_LTDC_HSYNC GPIO_LTDC_HSYNC_2 -#define GPIO_LTDC_DE GPIO_LTDC_DE_3 -#define GPIO_LTDC_CLK GPIO_LTDC_CLK_3 +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +/* LCD pinset */ + +#define GPIO_LTDC_PINS 24 /* 24-bit display */ + +#define GPIO_LTDC_R0 (GPIO_LTDC_R0_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R1 (GPIO_LTDC_R1_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R2 (GPIO_LTDC_R2_4|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R3 (GPIO_LTDC_R3_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R4 (GPIO_LTDC_R4_4|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R5 (GPIO_LTDC_R5_4|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R6 (GPIO_LTDC_R6_4|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R7 (GPIO_LTDC_R7_3|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_G0 (GPIO_LTDC_G0_2|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G1 (GPIO_LTDC_G1_2|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G2 (GPIO_LTDC_G2_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G3 (GPIO_LTDC_G3_4|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G4 (GPIO_LTDC_G4_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G5 (GPIO_LTDC_G5_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G6 (GPIO_LTDC_G6_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G7 (GPIO_LTDC_G7_3|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_B0 (GPIO_LTDC_B0_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B1 (GPIO_LTDC_B1_2|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B2 (GPIO_LTDC_B2_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B3 (GPIO_LTDC_B3_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B4 (GPIO_LTDC_B4_4|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B5 (GPIO_LTDC_B5_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B6 (GPIO_LTDC_B6_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B7 (GPIO_LTDC_B7_3|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_VSYNC (GPIO_LTDC_VSYNC_2|GPIO_SPEED_100MHz) +#define GPIO_LTDC_HSYNC (GPIO_LTDC_HSYNC_2|GPIO_SPEED_100MHz) +#define GPIO_LTDC_DE (GPIO_LTDC_DE_3|GPIO_SPEED_100MHz) +#define GPIO_LTDC_CLK (GPIO_LTDC_CLK_3|GPIO_SPEED_100MHz) /* QSPI pinset */ -#define GPIO_QSPI_CS GPIO_QUADSPI_BK1_NCS -#define GPIO_QSPI_IO0 GPIO_QUADSPI_BK1_IO0_3 -#define GPIO_QSPI_IO1 GPIO_QUADSPI_BK1_IO1_3 -#define GPIO_QSPI_IO2 GPIO_QUADSPI_BK1_IO2_1 -#define GPIO_QSPI_IO3 GPIO_QUADSPI_BK1_IO3_2 -#define GPIO_QSPI_SCK GPIO_QUADSPI_CLK - -/* SDMMC */ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 - * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif +#define GPIO_QSPI_CS (GPIO_QUADSPI_BK1_NCS|GPIO_SPEED_100MHz) +#define GPIO_QSPI_IO0 (GPIO_QUADSPI_BK1_IO0_3|GPIO_SPEED_100MHz) +#define GPIO_QSPI_IO1 (GPIO_QUADSPI_BK1_IO1_3|GPIO_SPEED_100MHz) +#define GPIO_QSPI_IO2 (GPIO_QUADSPI_BK1_IO2_1|GPIO_SPEED_100MHz) +#define GPIO_QSPI_IO3 (GPIO_QUADSPI_BK1_IO3_2|GPIO_SPEED_100MHz) +#define GPIO_QSPI_SCK (GPIO_QUADSPI_CLK|GPIO_SPEED_100MHz) /* SAI2 pinset */ -#if defined(CONFIG_STM32F7_SAI2) && defined(CONFIG_STM32F7_SAI2_A) -#define GPIO_SAI2_SD_A GPIO_SAI2_SD_A_2 -#define GPIO_SAI2_FS_A GPIO_SAI2_FS_A_2 -#define GPIO_SAI2_SCK_A GPIO_SAI2_SCK_A_2 -#define GPIO_SAI2_MCLK_A GPIO_SAI2_MCLK_A_2 -#define GPIO_SAI2_SD_B GPIO_SAI2_SD_B_4 - -#define DMACHAN_SAI2_A DMAMAP_SAI2_A -#define DMACHAN_SAI2_B DMAMAP_SAI2_B +#if defined(CONFIG_STM32F7_SAI2) && defined(CONFIG_STM32F7_SAI2_A) +# define GPIO_SAI2_SD_A (GPIO_SAI2_SD_A_2|GPIO_SPEED_100MHz) +# define GPIO_SAI2_FS_A (GPIO_SAI2_FS_A_2|GPIO_SPEED_100MHz) +# define GPIO_SAI2_SCK_A (GPIO_SAI2_SCK_A_2|GPIO_SPEED_100MHz) +# define GPIO_SAI2_MCLK_A (GPIO_SAI2_MCLK_A_2|GPIO_SPEED_100MHz) +# define GPIO_SAI2_SD_B (GPIO_SAI2_SD_B_4|GPIO_SPEED_100MHz) #else - -#define GPIO_SAI1_SD_B GPIO_SAI1_SD_B_1 -#define DMACHAN_SAI1_B DMAMAP_SAI1_B - -#endif +# define GPIO_SAI1_SD_B (GPIO_SAI1_SD_B_1|GPIO_SPEED_100MHz) #endif + +/* FMC */ + +#define GPIO_FMC_A0 (GPIO_FMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A1 (GPIO_FMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A2 (GPIO_FMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A3 (GPIO_FMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A4 (GPIO_FMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A5 (GPIO_FMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A6 (GPIO_FMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A7 (GPIO_FMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A8 (GPIO_FMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A9 (GPIO_FMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A10 (GPIO_FMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A11 (GPIO_FMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_NBL0 (GPIO_FMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_NBL1 (GPIO_FMC_NBL1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNRAS (GPIO_FMC_SDNRAS_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_BA0 (GPIO_FMC_BA0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_BA1 (GPIO_FMC_BA1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDCLK (GPIO_FMC_SDCLK_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNCAS (GPIO_FMC_SDNCAS_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D0 (GPIO_FMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D1 (GPIO_FMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D2 (GPIO_FMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D3 (GPIO_FMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D4 (GPIO_FMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D5 (GPIO_FMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D6 (GPIO_FMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D7 (GPIO_FMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D8 (GPIO_FMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D9 (GPIO_FMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D10 (GPIO_FMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D11 (GPIO_FMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D12 (GPIO_FMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D13 (GPIO_FMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D14 (GPIO_FMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D15 (GPIO_FMC_D15_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32F7_STM32F746G_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig index 13d1173067..15009b10c7 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig @@ -6,6 +6,7 @@ # modifications. # # CONFIG_SPI_CALLBACK is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig index b510300550..46614924b8 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig @@ -7,6 +7,7 @@ # # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/include/board.h b/boards/arm/stm32f7/stm32f769i-disco/include/board.h index c9d96c9599..e205200f06 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f769i-disco/include/board.h @@ -245,6 +245,36 @@ #define BOARD_FLASH_WAITSTATES 7 +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + /* LED definitions **********************************************************/ /* The STM32F769I-DISCO board has numerous LEDs but only one, LD1 located @@ -311,6 +341,44 @@ #define NUM_BUTTONS 1 #define BUTTON_USER_BIT (1 << BUTTON_USER) +/* LCD definitions **********************************************************/ + +/* LCD DISPLAY + * (work in progress as of 2017 07 19) + */ + +#define BOARD_LTDC_WIDTH 800 +#define BOARD_LTDC_HEIGHT 472 + +#define BOARD_LTDC_HSYNC 10 +#define BOARD_LTDC_HFP 10 +#define BOARD_LTDC_HBP 20 +#define BOARD_LTDC_VSYNC 2 +#define BOARD_LTDC_VFP 4 +#define BOARD_LTDC_VBP 2 + +#define BOARD_LTDC_GCR_PCPOL 0 +#define BOARD_LTDC_GCR_DEPOL 0 +#define BOARD_LTDC_GCR_VSPOL 0 +#define BOARD_LTDC_GCR_HSPOL 0 + +/* DMA Channel/Stream Selections ********************************************/ + +/* SDMMC */ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 + * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 + * + * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 + * DMAMAP_SDMMC2_2 = Channel 11, Stream 5 + */ + +#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 + /* Alternate function pin selections ****************************************/ /* USART6: @@ -327,8 +395,8 @@ * -- ----- --------- ----- */ -#define GPIO_USART6_RX GPIO_USART6_RX_1 -#define GPIO_USART6_TX GPIO_USART6_TX_1 +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* USART1: * USART1 is connected to the "Virtual Com Port" lines @@ -343,8 +411,8 @@ * -- ----- --------- ----- */ -#define GPIO_USART1_RX GPIO_USART1_RX_1 -#define GPIO_USART1_TX GPIO_USART1_TX_1 +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PWM * @@ -352,7 +420,7 @@ * be configured to output a pulse train using TIM1 CH4 on PA11. */ -#define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1 +#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) /* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins: * @@ -377,9 +445,15 @@ * receive errors can be detected using GPIO pin PD5 */ -#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2 -#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 -#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2 +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) /* I2C Mapping * I2C #4 is connected to the LCD daughter board @@ -388,54 +462,9 @@ * I2C4_SCL - PD12 * I2C4_SDA - PB7 */ -#define GPIO_I2C4_SCL GPIO_I2C4_SCL_1 -#define GPIO_I2C4_SDA GPIO_I2C4_SDA_5 - -/* SDMMC */ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 - * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 - * - * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 - * DMAMAP_SDMMC2_2 = Channel 11, Stream 5 - */ - -/* #define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 */ -#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif +#define GPIO_I2C4_SCL (GPIO_I2C4_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C4_SDA (GPIO_I2C4_SDA_5|GPIO_SPEED_50MHz) /* SDMMC2 Pin mapping * @@ -444,27 +473,12 @@ * D2 - PB3 * D3 - PB4 */ -#define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_2 -#define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_2 -#define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1 -#define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1 -/* LCD DISPLAY - * (work in progress as of 2017 07 19) - */ -#define BOARD_LTDC_WIDTH 800 -#define BOARD_LTDC_HEIGHT 472 - -#define BOARD_LTDC_HSYNC 10 -#define BOARD_LTDC_HFP 10 -#define BOARD_LTDC_HBP 20 -#define BOARD_LTDC_VSYNC 2 -#define BOARD_LTDC_VFP 4 -#define BOARD_LTDC_VBP 2 - -#define BOARD_LTDC_GCR_PCPOL 0 -#define BOARD_LTDC_GCR_DEPOL 0 -#define BOARD_LTDC_GCR_VSPOL 0 -#define BOARD_LTDC_GCR_HSPOL 0 +#define GPIO_SDMMC2_CK (GPIO_SDMMC2_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_CMD (GPIO_SDMMC2_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D0 (GPIO_SDMMC2_D0_2|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D1 (GPIO_SDMMC2_D1_2|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_1|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_1|GPIO_SPEED_50MHz) #endif /* __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig index 230a257c1e..b7a15b33c4 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 3fe65fdc76..2da74986f4 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -248,6 +248,36 @@ #define BOARD_FLASH_WAITSTATES 7 +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + /* LED definitions **********************************************************/ /* The STM32F777ZIT6-MEADOW board has numerous LEDs but only one, LD1 @@ -323,6 +353,44 @@ #define NUM_BUTTONS 1 #define BUTTON_USER_BIT (1 << BUTTON_USER) +/* LED definitions **********************************************************/ + +/* LCD DISPLAY + * (work in progress as of 2017 07 19) + */ + +#define BOARD_LTDC_WIDTH 800 +#define BOARD_LTDC_HEIGHT 472 + +#define BOARD_LTDC_HSYNC 10 +#define BOARD_LTDC_HFP 10 +#define BOARD_LTDC_HBP 20 +#define BOARD_LTDC_VSYNC 2 +#define BOARD_LTDC_VFP 4 +#define BOARD_LTDC_VBP 2 + +#define BOARD_LTDC_GCR_PCPOL 0 +#define BOARD_LTDC_GCR_DEPOL 0 +#define BOARD_LTDC_GCR_VSPOL 0 +#define BOARD_LTDC_GCR_HSPOL 0 + +/* DMA Channel/Stream Selections ********************************************/ + +/* SDMMC */ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 + * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 + * + * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 + * DMAMAP_SDMMC2_2 = Channel 11, Stream 5 + */ + +#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 + /* Alternate function pin selections ****************************************/ /* USART6: @@ -340,8 +408,8 @@ * -- ----- --------- ----- */ -#define GPIO_USART6_RX GPIO_USART6_RX_1 -#define GPIO_USART6_TX GPIO_USART6_TX_1 +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* USART1: * USART1 is connected to the "Virtual Com Port" lines @@ -356,8 +424,8 @@ * -- ----- --------- ----- */ -#define GPIO_USART1_RX GPIO_USART1_RX_3 -#define GPIO_USART1_TX GPIO_USART1_TX_3 +#define GPIO_USART1_RX (GPIO_USART1_RX_3|GPIO_SPEED_100MHz) +#define GPIO_USART1_TX (GPIO_USART1_TX_3|GPIO_SPEED_100MHz) /* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins: * @@ -382,9 +450,15 @@ * receive errors can be detected using GPIO pin PD5 */ -#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2 -#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 -#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2 +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) /* I2C Mapping * I2C #4 is connected to the LCD daughter board @@ -393,8 +467,8 @@ * I2C4_SCL - PD12 * I2C4_SDA - PB7 */ -#define GPIO_I2C4_SCL GPIO_I2C4_SCL_1 -#define GPIO_I2C4_SDA GPIO_I2C4_SDA_5 +#define GPIO_I2C4_SCL (GPIO_I2C4_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C4_SDA (GPIO_I2C4_SDA_5|GPIO_SPEED_50MHz) /* QSPI Mapping */ @@ -405,52 +479,6 @@ #define GPIO_QSPI_IO3 (GPIO_QUADSPI_BK1_IO3_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) #define GPIO_QSPI_SCK (GPIO_QUADSPI_CLK_1 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) -/* SDMMC */ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 - * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 - * - * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 - * DMAMAP_SDMMC2_2 = Channel 11, Stream 5 - */ - -/* #define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 */ -#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif - /* SDMMC2 Pin mapping * * D0 - PG9 @@ -458,33 +486,18 @@ * D2 - PB3 * D3 - PB4 */ -#define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_2 -#define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_2 -#define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1 -#define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1 - -/* FMC - SDRAM */ - -#define GPIO_FMC_SDCKE1 GPIO_FMC_SDCKE1_1 -#define GPIO_FMC_SDNE1 GPIO_FMC_SDNE1_1 -#define GPIO_FMC_SDNWE GPIO_FMC_SDNWE_1 -/* LCD DISPLAY - * (work in progress as of 2017 07 19) - */ -#define BOARD_LTDC_WIDTH 800 -#define BOARD_LTDC_HEIGHT 472 +#define GPIO_SDMMC2_CK (GPIO_SDMMC2_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_CMD (GPIO_SDMMC2_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D0 (GPIO_SDMMC2_D0_2|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D1 (GPIO_SDMMC2_D1_2|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_1|GPIO_SPEED_50MHz) +#define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_1|GPIO_SPEED_50MHz) -#define BOARD_LTDC_HSYNC 10 -#define BOARD_LTDC_HFP 10 -#define BOARD_LTDC_HBP 20 -#define BOARD_LTDC_VSYNC 2 -#define BOARD_LTDC_VFP 4 -#define BOARD_LTDC_VBP 2 +/* FMC - SDRAM */ -#define BOARD_LTDC_GCR_PCPOL 0 -#define BOARD_LTDC_GCR_DEPOL 0 -#define BOARD_LTDC_GCR_VSPOL 0 -#define BOARD_LTDC_GCR_HSPOL 0 +#define GPIO_FMC_SDCKE1 (GPIO_FMC_SDCKE1_1|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNE1 (GPIO_FMC_SDNE1_1|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_1|GPIO_SPEED_100MHz) #endif /* __BOARDS_ARM_STM32F777ZIT6_MEADOW_INCLUDE_BOARD_H */
