pussuw commented on code in PR #9486:
URL: https://github.com/apache/nuttx/pull/9486#discussion_r1219592224
##########
arch/risc-v/src/common/riscv_fpu.S:
##########
@@ -57,18 +61,95 @@
* Returned Value:
* This function does not return anything explicitly.
*
-
************************************************************************************/
+ ****************************************************************************/
.type riscv_fpuconfig, function
riscv_fpuconfig:
- li a0, MSTATUS_FS_INIT
- csrs CSR_STATUS, a0
+ li a0, MSTATUS_FS_INIT
+ csrs CSR_STATUS, a0
+
+ fsflags zero
+ fsrm zero
+
+ fence.i
+ ret
+
+/****************************************************************************
+ * Name: riscv_savefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), save the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void riscv_savefpu(uintptr_t *regs, uintptr_t *fregs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the integer registers that contain the status
+ * fregs - A pointer to the register save area in which to save the
+ * floating point registers
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+ .type riscv_savefpu, function
+
+riscv_savefpu:
+
+ REGLOAD t0, REG_INT_CTX(a0)
+ li t1, MSTATUS_FS
+ and t2, t0, t1
+ li t1, MSTATUS_FS_DIRTY
+ bne t2, t1, 1f
Review Comment:
```
Just a reminder to self:
#ifdef CONFIG_ARCH_RISCV_LAZYFPU
bne t2, t1, 1f
#else
blt t2, t1, 1f
#endif
```
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