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xiaoxiang pushed a commit to branch master
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The following commit(s) were added to refs/heads/master by this push:
new c9f610f44f stm32f777zit6-meadow: Fix external RAM pinout and add board
profile
c9f610f44f is described below
commit c9f610f44f29d484f043c7ccdde016cd08a08a99
Author: Alan Carvalho de Assis <[email protected]>
AuthorDate: Sat Jun 17 16:17:42 2023 -0300
stm32f777zit6-meadow: Fix external RAM pinout and add board profile
This patch will fix an issue that was preventing the stm32f7 board
from working with external SDRAM memory.
---
.../stm32f777zit6-meadow/configs/sdram/defconfig | 48 +++
.../stm32f7/stm32f777zit6-meadow/include/board.h | 46 ++-
.../arm/stm32f7/stm32f777zit6-meadow/src/Makefile | 9 +
.../stm32f7/stm32f777zit6-meadow/src/stm32_boot.c | 15 +-
.../stm32f777zit6-meadow/src/stm32_extmem.c | 102 +++---
.../stm32f7/stm32f777zit6-meadow/src/stm32_usb.c | 341 +++++++++++++++++++++
.../src/stm32f777zit6-meadow.h | 4 +
7 files changed, 521 insertions(+), 44 deletions(-)
diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig
b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig
new file mode 100644
index 0000000000..6f41db2e35
--- /dev/null
+++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig
@@ -0,0 +1,48 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed
.config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that
includes your
+# modifications.
+#
+# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="stm32f777zit6-meadow"
+CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y
+CONFIG_ARCH_CHIP="stm32f7"
+CONFIG_ARCH_CHIP_STM32F777ZI=y
+CONFIG_ARCH_CHIP_STM32F7=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=43103
+CONFIG_BUILTIN=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_HEAP2_BASE=0xc0000000
+CONFIG_HEAP2_SIZE=33554432
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MM_REGIONS=3
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SPI=y
+CONFIG_START_DAY=14
+CONFIG_STM32F7_EXTERNAL_RAM=y
+CONFIG_STM32F7_FMC=y
+CONFIG_STM32F7_USART1=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_RAMTEST=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART1_SERIAL_CONSOLE=y
diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h
b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h
index b9fd9c35d8..868f88688c 100644
--- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h
+++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h
@@ -494,10 +494,54 @@
#define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_1|GPIO_SPEED_50MHz)
#define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_1|GPIO_SPEED_50MHz)
+/* OTGFS */
+
+#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz)
+#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz)
+#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz)
+
/* FMC - SDRAM */
+#define GPIO_FMC_A0 (GPIO_FMC_A0_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A1 (GPIO_FMC_A1_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A2 (GPIO_FMC_A2_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A3 (GPIO_FMC_A3_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A4 (GPIO_FMC_A4_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A5 (GPIO_FMC_A5_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A6 (GPIO_FMC_A6_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A7 (GPIO_FMC_A7_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A8 (GPIO_FMC_A8_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A9 (GPIO_FMC_A9_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A10 (GPIO_FMC_A10_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A11 (GPIO_FMC_A11_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_A12 (GPIO_FMC_A12_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_BA0 (GPIO_FMC_BA0_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_BA1 (GPIO_FMC_BA1_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D0 (GPIO_FMC_D0_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D1 (GPIO_FMC_D1_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D2 (GPIO_FMC_D2_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D3 (GPIO_FMC_D3_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D4 (GPIO_FMC_D4_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D5 (GPIO_FMC_D5_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D6 (GPIO_FMC_D6_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D7 (GPIO_FMC_D7_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D8 (GPIO_FMC_D8_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D9 (GPIO_FMC_D9_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D10 (GPIO_FMC_D10_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D11 (GPIO_FMC_D11_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D12 (GPIO_FMC_D12_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D13 (GPIO_FMC_D13_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D14 (GPIO_FMC_D14_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_D15 (GPIO_FMC_D15_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_NBL0 (GPIO_FMC_NBL0_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_NBL1 (GPIO_FMC_NBL1_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_SDCLK (GPIO_FMC_SDCLK_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_SDCKE0 (GPIO_FMC_SDCKE0_3|GPIO_SPEED_100MHz)
#define GPIO_FMC_SDCKE1 (GPIO_FMC_SDCKE1_1|GPIO_SPEED_100MHz)
+#define GPIO_FMC_SDNE0 (GPIO_FMC_SDNE0_3|GPIO_SPEED_100MHz)
#define GPIO_FMC_SDNE1 (GPIO_FMC_SDNE1_1|GPIO_SPEED_100MHz)
-#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_1|GPIO_SPEED_100MHz)
+#define GPIO_FMC_SDNCAS (GPIO_FMC_SDNCAS_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_SDNRAS (GPIO_FMC_SDNRAS_0|GPIO_SPEED_100MHz)
+#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_3|GPIO_SPEED_100MHz)
#endif /* __BOARDS_ARM_STM32F777ZIT6_MEADOW_INCLUDE_BOARD_H */
diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Makefile
b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Makefile
index 49dff624e0..b34c3bb61b 100644
--- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Makefile
+++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Makefile
@@ -34,6 +34,9 @@ endif
ifeq ($(CONFIG_BOARDCTL),y)
CSRCS += stm32_appinitialize.c
+ifeq ($(CONFIG_BOARDCTL_IOCTL),y)
+CSRCS += stm32_ioctl.c
+endif
endif
ifeq ($(CONFIG_PWM),y)
@@ -48,4 +51,10 @@ ifeq ($(CONFIG_STM32F7_FMC),y)
CSRCS += stm32_extmem.c
endif
+ifeq ($(CONFIG_STM32F7_OTGFS),y)
+CSRCS += stm32_usb.c
+else ifeq ($(CONFIG_STM32F7_OTGFSHS),y)
+CSRCS += stm32_usb.c
+endif
+
include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c
b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c
index c9371cfba4..9561be7401 100644
--- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c
+++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c
@@ -129,9 +129,6 @@ void board_late_initialize(void)
#ifdef CONFIG_STM32F7_QUADSPI
FAR struct qspi_dev_s *qspi;
FAR struct mtd_dev_s *mtd;
-#endif
-
-#ifdef CONFIG_STM32F7_QUADSPI
struct qspi_meminfo_s meminfo;
@@ -167,9 +164,15 @@ void board_late_initialize(void)
stm32f7_qspi_enter_memorymapped(qspi, &meminfo, 80000000);
stm32_mpu_uheap((uintptr_t)0x90000000, 0x4000000);
- }
-
#endif
- stm32_bringup();
+#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_BOARDCTL)
+ /* Perform NSH initialization here instead of from the NSH. This
+ * alternative NSH initialization is necessary when NSH is ran in
+ * user-space but the initialization function must run in kernel space.
+ */
+
+ board_app_initialize();
+#endif
+}
#endif
diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c
b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c
index 53466475c9..cb2325ee8a 100644
--- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c
+++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c
@@ -52,15 +52,16 @@
#define STM32_FMC_NADDRCONFIGS 23
#define STM32_FMC_NDATACONFIGS 16
-#define STM32_SDRAM_CLKEN FMC_SDRAM_MODE_CMD_CLK_ENABLE |
FMC_SDRAM_CMD_BANK_1
-#define STM32_SDRAM_PALL FMC_SDRAM_MODE_CMD_PALL | FMC_SDRAM_CMD_BANK_1
-#define STM32_SDRAM_REFRESH FMC_SDRAM_MODE_CMD_AUTO_REFRESH |
FMC_SDRAM_CMD_BANK_1 |\
- (3 << FMC_SDRAM_AUTO_REFRESH_SHIFT)
-#define STM32_SDRAM_MODEREG FMC_SDRAM_MODE_CMD_LOAD_MODE |
FMC_SDRAM_CMD_BANK_1 |\
- FMC_SDRAM_MODEREG_BURST_LENGTH_1 | \
- FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
- FMC_SDRAM_MODEREG_CAS_LATENCY_3 |\
- FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE
+#define STM32_SDRAM_CLKEN FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_CLK_ENABLE
+#define STM32_SDRAM_PALL FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_PALL
+#define STM32_SDRAM_REFRESH FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_AUTO_REFRESH |\
+ FMC_SDCMR_NRFS(8)
+#define STM32_SDRAM_MODEREG FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_LOAD_MODE |\
+ FMC_SDCMR_MRD_BURST_LENGTH_1 | \
+ FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |\
+ FMC_SDCMR_MRD_CAS_LATENCY_3 |\
+ FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |\
+ FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE
/****************************************************************************
* Public Data
@@ -74,15 +75,15 @@ static const uint32_t
g_addressconfig[STM32_FMC_NADDRCONFIGS] =
GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9,
GPIO_FMC_A10, GPIO_FMC_A11, GPIO_FMC_A12,
- GPIO_FMC_SDCKE0_3, GPIO_FMC_SDNE0_3, GPIO_FMC_SDNWE_3, GPIO_FMC_NBL0,
- GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
- GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS
+ GPIO_FMC_SDCKE0, GPIO_FMC_SDNE0, GPIO_FMC_SDNWE, GPIO_FMC_NBL0,
+ GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
+ GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS
};
static const uint32_t g_dataconfig[STM32_FMC_NDATACONFIGS] =
{
- GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4,
- GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9,
+ GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4,
+ GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9,
GPIO_FMC_D10, GPIO_FMC_D11, GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14,
GPIO_FMC_D15
};
@@ -115,6 +116,33 @@ static void stm32_extmemgpios(const uint32_t *gpios, int
ngpios)
}
}
+/****************************************************************************
+ * Name: stm32_sdramcommand
+ *
+ * Description:
+ * Initialize data line GPIOs for external memory access
+ */
+
+static void stm32_sdramcommand(uint32_t command)
+{
+ uint32_t regval;
+ volatile uint32_t timeout = 0xffff;
+
+ regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
+ while ((regval != 0) && timeout-- > 0)
+ {
+ regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
+ }
+
+ putreg32(command, STM32_FMC_SDCMR);
+ timeout = 0xffff;
+ regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
+ while ((regval != 0) && timeout-- > 0)
+ {
+ regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
+ }
+}
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -129,7 +157,7 @@ static void stm32_extmemgpios(const uint32_t *gpios, int
ngpios)
void stm32_sdram_initialize(void)
{
- uint32_t val;
+ uint32_t regval;
volatile int count;
/* Enable GPIOs as FMC / memory pins */
@@ -148,37 +176,37 @@ void stm32_sdram_initialize(void)
* All timings from the datasheet for Speedgrade -7 (=7ns)
*/
- putreg32(FMC_SDRAM_CR_RPIPE_1 |
- FMC_SDRAM_CR_SDCLK_2X |
- FMC_SDRAM_CR_CASLAT_3 |
- FMC_SDRAM_CR_BANKS_4 |
- FMC_SDRAM_CR_WIDTH_16 |
- FMC_SDRAM_CR_ROWBITS_13 |
- FMC_SDRAM_CR_COLBITS_9,
+ putreg32(FMC_SDCR_RPIPE_1 |
+ FMC_SDCR_SDCLK_2X |
+ FMC_SDCR_CASLAT_3 |
+ FMC_SDCR_BANKS_4 |
+ FMC_SDCR_WIDTH_16 |
+ FMC_SDCR_ROWBITS_13 |
+ FMC_SDCR_COLBITS_9,
STM32_FMC_SDCR1);
- putreg32(FMC_SDRAM_CR_RPIPE_1 |
- FMC_SDRAM_CR_SDCLK_2X |
- FMC_SDRAM_CR_CASLAT_3 |
- FMC_SDRAM_CR_BANKS_4 |
- FMC_SDRAM_CR_WIDTH_16 |
- FMC_SDRAM_CR_ROWBITS_13 |
- FMC_SDRAM_CR_COLBITS_9,
+ putreg32(FMC_SDCR_RPIPE_1 |
+ FMC_SDCR_SDCLK_2X |
+ FMC_SDCR_CASLAT_3 |
+ FMC_SDCR_BANKS_4 |
+ FMC_SDCR_WIDTH_16 |
+ FMC_SDCR_ROWBITS_13 |
+ FMC_SDCR_COLBITS_9,
STM32_FMC_SDCR2);
- putreg32((2 << FMC_SDRAM_TR_TRCD_SHIFT) | /* tRCD min = 15ns */
- (2 << FMC_SDRAM_TR_TRP_SHIFT) | /* tRP min = 15ns */
- (2 << FMC_SDRAM_TR_TWR_SHIFT) | /* tWR = 2CLK */
- (7 << FMC_SDRAM_TR_TRC_SHIFT) | /* tRC min = 63ns */
- (4 << FMC_SDRAM_TR_TRAS_SHIFT) | /* tRAS min = 42ns */
- (7 << FMC_SDRAM_TR_TXSR_SHIFT) | /* tXSR min = 70ns */
- (2 << FMC_SDRAM_TR_TMRD_SHIFT), /* tMRD = 2CLK */
+ putreg32((2 << FMC_SDTR_TRCD_SHIFT) | /* tRCD min = 15ns */
+ (2 << FMC_SDTR_TRP_SHIFT) | /* tRP min = 15ns */
+ (2 << FMC_SDTR_TWR_SHIFT) | /* tWR = 2CLK */
+ (7 << FMC_SDTR_TRC_SHIFT) | /* tRC min = 63ns */
+ (4 << FMC_SDTR_TRAS_SHIFT) | /* tRAS min = 42ns */
+ (7 << FMC_SDTR_TXSR_SHIFT) | /* tXSR min = 70ns */
+ (2 << FMC_SDTR_TMRD_SHIFT), /* tMRD = 2CLK */
STM32_FMC_SDTR1);
/* SDRAM Initialization sequence */
stm32_sdramcommand(STM32_SDRAM_CLKEN); /* Clock enable command */
- for (count = 0; count < 10000; count++) ; /* Delay */
+ for (count = 0; count < 10000; count++); /* Delay */
stm32_sdramcommand(STM32_SDRAM_PALL); /* Precharge ALL command */
stm32_sdramcommand(STM32_SDRAM_REFRESH); /* Auto refresh command */
stm32_sdramcommand(STM32_SDRAM_MODEREG); /* Mode Register program */
diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c
b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c
new file mode 100644
index 0000000000..f54c5dc0da
--- /dev/null
+++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c
@@ -0,0 +1,341 @@
+/****************************************************************************
+ * boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <sched.h>
+#include <errno.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/kthread.h>
+#include <nuttx/usb/usbdev.h>
+#include <nuttx/usb/usbhost.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include <arch/board/board.h>
+
+#include "arm_internal.h"
+#include "stm32_otg.h"
+#include "stm32_gpio.h"
+#include "stm32f777zit6-meadow.h"
+
+#ifdef CONFIG_STM32F7_OTGFS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
+# define HAVE_USB 1
+#else
+# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor
CONFIG_USBHOST"
+# undef HAVE_USB
+#endif
+
+#ifndef CONFIG_STM32F7F4DISCO_USBHOST_PRIO
+# define CONFIG_STM32F7F4DISCO_USBHOST_PRIO 100
+#endif
+
+#ifndef CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE
+# define CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE 1024
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+static struct usbhost_connection_s *g_usbconn;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: usbhost_waiter
+ *
+ * Description:
+ * Wait for USB devices to be connected.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+static int usbhost_waiter(int argc, char *argv[])
+{
+ struct usbhost_hubport_s *hport;
+
+ uinfo("Running\n");
+ for (; ; )
+ {
+ /* Wait for the device to change state */
+
+ DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
+ uinfo("%s\n", hport->connected ? "connected" : "disconnected");
+
+ /* Did we just become connected? */
+
+ if (hport->connected)
+ {
+ /* Yes.. enumerate the newly connected device */
+
+ CONN_ENUMERATE(g_usbconn, hport);
+ }
+ }
+
+ /* Keep the compiler from complaining */
+
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ * Called from stm32_usbinitialize very early in inialization to setup
+ * USB-related GPIO pins for the STM32F4Discovery board.
+ *
+ ****************************************************************************/
+
+void stm32_usbinitialize(void)
+{
+ /* The OTG FS has an internal soft pull-up.
+ * No GPIO configuration is required
+ */
+
+ /* Configure the OTG FS VBUS sensing GPIO,
+ * Power On, and Overcurrent GPIOs
+ */
+
+#ifdef CONFIG_STM32F7_OTGFS
+ stm32_configgpio(GPIO_OTGFS_VBUS);
+# ifdef CONFIG_USBHOST
+ stm32_configgpio(GPIO_OTGFS_PWRON);
+ stm32_configgpio(GPIO_OTGFS_OVER);
+# endif
+#endif
+ stm32_configgpio(GPIO_OTGFS_VBUS);
+
+#ifdef CONFIG_USBHOST
+ stm32_configgpio(GPIO_OTGFS_PWRON);
+ stm32_configgpio(GPIO_OTGFS_OVER);
+#endif
+#endif
+}
+
+/****************************************************************************
+ * Name: stm32_usbhost_initialize
+ *
+ * Description:
+ * Called at application startup time to initialize the USB host
+ * functionality.
+ * This function will start a thread that will monitor for device
+ * connection/disconnection events.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+int stm32_usbhost_initialize(void)
+{
+ int ret;
+
+ /* First, register all of the class drivers needed to support the drivers
+ * that we care about:
+ */
+
+ uinfo("Register class drivers\n");
+
+#ifdef CONFIG_USBHOST_HUB
+ /* Initialize USB hub class support */
+
+ ret = usbhost_hub_initialize();
+ if (ret < 0)
+ {
+ uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_USBHOST_MSC
+ /* Register the USB mass storage class class */
+
+ ret = usbhost_msc_initialize();
+ if (ret != OK)
+ {
+ uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_USBHOST_CDCACM
+ /* Register the CDC/ACM serial class */
+
+ ret = usbhost_cdcacm_initialize();
+ if (ret != OK)
+ {
+ uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_USBHOST_HIDKBD
+ /* Initialize the HID keyboard class */
+
+ ret = usbhost_kbdinit();
+ if (ret != OK)
+ {
+ uerr("ERROR: Failed to register the HID keyboard class\n");
+ }
+#endif
+
+#ifdef CONFIG_USBHOST_HIDMOUSE
+ /* Initialize the HID mouse class */
+
+ ret = usbhost_mouse_init();
+ if (ret != OK)
+ {
+ uerr("ERROR: Failed to register the HID mouse class\n");
+ }
+#endif
+
+ /* Then get an instance of the USB host interface */
+
+ uinfo("Initialize USB host\n");
+ g_usbconn = stm32_otgfshost_initialize(0);
+ if (g_usbconn)
+ {
+ /* Start a thread to handle device connection. */
+
+ uinfo("Start usbhost_waiter\n");
+
+ ret = kthread_create("usbhost", CONFIG_STM32F7F4DISCO_USBHOST_PRIO,
+ CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE,
+ (main_t)usbhost_waiter, (char * const *)NULL);
+ return ret < 0 ? -ENOEXEC : OK;
+ }
+
+ return -ENODEV;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbhost_vbusdrive
+ *
+ * Description:
+ * Enable/disable driving of VBUS 5V output. This function must be
+ * provided be each platform that implements the STM32 OTG FS host
+ * interface
+ *
+ * "On-chip 5 V VBUS generation is not supported. For this reason, a
+ * charge pump or, if 5 V are available on the application board, a
+ * basic power switch, must be added externally to drive the 5 V VBUS
+ * line. The external charge pump can be driven by any GPIO output.
+ * When the application decides to power on VBUS using the chosen GPIO,
+ * it must also set the port power bit in the host port control and
+ * status register (PPWR bit in OTG_FS_HPRT).
+ *
+ * "The application uses this field to control power to this port,
+ * and the core clears this bit on an overcurrent condition."
+ *
+ * Input Parameters:
+ * iface - For future growth to handle multiple USB host interface.
+ * Should be zero.
+ * enable - true: enable VBUS power; false: disable VBUS power
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+void stm32_usbhost_vbusdrive(int iface, bool enable)
+{
+ DEBUGASSERT(iface == 0);
+
+ syslog(LOG_INFO, "USB Drive %i %i", iface, (int)enable);
+
+ if (enable)
+ {
+ /* Enable the Power Switch by driving the enable pin low */
+
+ stm32_gpiowrite(GPIO_OTGFS_PWRON, false);
+ }
+ else
+ {
+ /* Disable the Power Switch by driving the enable pin high */
+
+ stm32_gpiowrite(GPIO_OTGFS_PWRON, true);
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_setup_overcurrent
+ *
+ * Description:
+ * Setup to receive an interrupt-level callback if an overcurrent
+ * condition is detected.
+ *
+ * Input Parameters:
+ * handler - New overcurrent interrupt handler
+ * arg - The argument provided for the interrupt handler
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. Otherwise, a negated errno value
+ * is returned to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+int stm32_setup_overcurrent(xcpt_t handler, void *arg)
+{
+ return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbsuspend
+ *
+ * Description:
+ * Board logic must provide the stm32_usbsuspend logic if the USBDEV
+ * driver is used. This function is called whenever the USB enters or
+ * leaves suspend mode. This is an opportunity for the board logic to
+ * shutdown clocks, power, etc. while the USB is suspended.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBDEV
+void stm32_usbsuspend(struct usbdev_s *dev, bool resume)
+{
+ uinfo("resume: %d\n", resume);
+}
+#endif
+
+#endif /* CONFIG_STM32F7_OTGFS */
diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h
b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h
index 58572a2f45..cc099feee5 100644
--- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h
+++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h
@@ -76,6 +76,9 @@
#define GPIO_SCHED_RUNNING (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |
GPIO_OUTPUT_CLEAR | \
GPIO_PORTJ | GPIO_PIN0)
+#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\
+ GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
+
/****************************************************************************
* Public data
****************************************************************************/
@@ -147,6 +150,7 @@ void arch_sporadic_initialize(void);
****************************************************************************/
#ifdef CONFIG_STM32F7_FMC
+void stm32_sdram_initialize(void);
void stm32_disablefmc(void);
#endif
