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new 4969f8faf9 risc-v Toolchain.defs compatibility.
Reference:https://xpack.github.io/blog/2022/05/18/riscv-none-elf-gcc-v12-1-0-2-released/
4969f8faf9 is described below
commit 4969f8faf9121b8d76b01ef9c14691479deb83b6
Author: tjwu1217 <[email protected]>
AuthorDate: Mon Jun 26 02:36:09 2023 +0000
risc-v Toolchain.defs compatibility.
Reference:https://xpack.github.io/blog/2022/05/18/riscv-none-elf-gcc-v12-1-0-2-released/
RISC-V ISA updates
Compared to previous releases, starting from 12.x, the compiler implements
the new RISC-V ISA, which introduces an incompatibility issue, and builds might
throw error messages like unrecognized opcode csrr.
The reason is that csr read/write (csrr*/csrw*) instructions and fence.i
instruction were separated from the I extension, becoming two standalone
extensions: Zicsr and Zifencei.
The solution is to add _zicsr and/or _zifencei to the -march option, e.g.
-march=rv32imac becomes -march=rv32imac_zicsr_zifencei.
---
arch/risc-v/src/common/Toolchain.defs | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/risc-v/src/common/Toolchain.defs
b/arch/risc-v/src/common/Toolchain.defs
index 6c8fd79bae..ca821831bd 100644
--- a/arch/risc-v/src/common/Toolchain.defs
+++ b/arch/risc-v/src/common/Toolchain.defs
@@ -150,6 +150,11 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
ARCHRVISAD = d
endif
+ GCC_VERSION = ${shell $(CROSSDEV)gcc --version | grep gcc | grep -oE
'[0-9]+\.[0-9]+\.[0-9]+' | tail -n 1 | cut -d"." -f1 }
+ ifeq ($(shell expr $(GCC_VERSION) \>= 12), 1)
+ ARCHRVISAZ = _zicsr_zifencei
+ endif
+
# Detect abi type
ifeq ($(CONFIG_ARCH_RV32),y)
@@ -164,7 +169,7 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
# Construct arch flags
- ARCHCPUEXTFLAGS =
i$(ARCHRVISAM)$(ARCHRVISAA)$(ARCHRVISAF)$(ARCHRVISAD)$(ARCHRVISAC)
+ ARCHCPUEXTFLAGS =
i$(ARCHRVISAM)$(ARCHRVISAA)$(ARCHRVISAF)$(ARCHRVISAD)$(ARCHRVISAC)$(ARCHRVISAZ)
ARCHCPUFLAGS = -march=$(ARCHTYPE)$(ARCHCPUEXTFLAGS)
# Construct arch abi flags
