[nuttx] branch releases/12.2 updated: 1.arch/arm/src/stm32/stm32_rtcounter.c up_rtc_initialize Possible stall 2.arch/arm/src/stm32/stm32_rtcounter.c up_rtc_settime memory hardfault

[xiaoxiang]

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch releases/12.2
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/releases/12.2 by this push:
     new 9e719bbbb7 1.arch/arm/src/stm32/stm32_rtcounter.c   up_rtc_initialize 
Possible stall 2.arch/arm/src/stm32/stm32_rtcounter.c up_rtc_settime memory 
hardfault
9e719bbbb7 is described below

commit 9e719bbbb7523d3f4bc9a92a16c9175550a823d9
Author: lpxiao <lp.x...@hotmail.com>
AuthorDate: Wed Jul 5 22:17:53 2023 +0800

    1.arch/arm/src/stm32/stm32_rtcounter.c   up_rtc_initialize Possible stall 
2.arch/arm/src/stm32/stm32_rtcounter.c up_rtc_settime memory hardfault
---
 arch/arm/src/stm32/stm32_rtcounter.c | 65 ++++++++++++++++++++++--------------
 1 file changed, 40 insertions(+), 25 deletions(-)

diff --git a/arch/arm/src/stm32/stm32_rtcounter.c 
b/arch/arm/src/stm32/stm32_rtcounter.c
index 3a3d54600b..4fddcc5ec4 100644
--- a/arch/arm/src/stm32/stm32_rtcounter.c
+++ b/arch/arm/src/stm32/stm32_rtcounter.c
@@ -172,10 +172,10 @@ volatile bool g_rtc_enabled = false;
  ****************************************************************************/
 
 /****************************************************************************
- * Name: stm32_rtc_beginwr
+ * Name: stm32_rtc_waitlasttask
  *
  * Description:
- *   Enter configuration mode
+ *   wait task done
  *
  * Input Parameters:
  *   None
@@ -185,7 +185,7 @@ volatile bool g_rtc_enabled = false;
  *
  ****************************************************************************/
 
-static inline void stm32_rtc_beginwr(void)
+static inline void stm32_rtc_waitlasttask(void)
 {
   /* Previous write is done? */
 
@@ -193,6 +193,25 @@ static inline void stm32_rtc_beginwr(void)
     {
       stm32_waste();
     }
+}
+
+/****************************************************************************
+ * Name: stm32_rtc_beginwr
+ *
+ * Description:
+ *   Enter configuration mode
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void stm32_rtc_beginwr(void)
+{
+  stm32_rtc_waitlasttask();
 
   /* Enter Config mode, Set Value and Exit */
 
@@ -216,13 +235,7 @@ static inline void stm32_rtc_beginwr(void)
 static inline void stm32_rtc_endwr(void)
 {
   modifyreg16(STM32_RTC_CRL, RTC_CRL_CNF, 0);
-
-  /* Wait for the write to actually reach RTC registers */
-
-  while ((getreg16(STM32_RTC_CRL) & RTC_CRL_RTOFF) == 0)
-    {
-      stm32_waste();
-    }
+  stm32_rtc_waitlasttask();
 }
 
 /****************************************************************************
@@ -384,6 +397,15 @@ int up_rtc_initialize(void)
       putreg16(RTC_MAGIC, RTC_MAGIC_REG);
     }
 
+  modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
+
+  /* Wait for the LSE clock to be ready */
+
+  while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
+    {
+      stm32_waste();
+    }
+
   /* Select the lower power external 32,768Hz (Low-Speed External, LSE)
    * oscillator as RTC Clock Source and enable the Clock.
    */
@@ -393,12 +415,10 @@ int up_rtc_initialize(void)
   /* Enable RTC and wait for RSF */
 
   modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
-
-  /* TODO: Possible stall?
-   * should we set the timeout period? and return with -1
-   */
+  stm32_rtc_waitlasttask();
 
   stm32_rtc_wait4rsf();
+  stm32_rtc_waitlasttask();
 
   /* Configure prescaler, note that these are write-only registers */
 
@@ -408,6 +428,7 @@ int up_rtc_initialize(void)
   stm32_rtc_endwr();
 
   stm32_rtc_wait4rsf();
+  stm32_rtc_waitlasttask();
 
 #ifdef CONFIG_RTC_HIRES
   /* Enable overflow interrupt - alarm interrupt is enabled in
@@ -631,7 +652,6 @@ int up_rtc_settime(const struct timespec *tp)
 {
   struct rtc_regvals_s regvals;
   irqstate_t flags;
-  uint16_t cntl;
 
   /* Break out the time values */
 
@@ -646,16 +666,11 @@ int up_rtc_settime(const struct timespec *tp)
    * register (hi-res mode only)
    */
 
-  do
-    {
-      stm32_rtc_beginwr();
-      putreg16(RTC_MAGIC, RTC_MAGIC_TIME_SET);
-      putreg16(regvals.cnth, STM32_RTC_CNTH);
-      putreg16(regvals.cntl, STM32_RTC_CNTL);
-      cntl = getreg16(STM32_RTC_CNTL);
-      stm32_rtc_endwr();
-    }
-  while (cntl != regvals.cntl);
+  stm32_rtc_beginwr();
+  putreg16(regvals.cnth, STM32_RTC_CNTH);
+  putreg16(regvals.cntl, STM32_RTC_CNTL);
+  stm32_rtc_endwr();
+  putreg16(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG);
 
 #ifdef CONFIG_RTC_HIRES
   putreg16(regvals.ovf, RTC_TIMEMSB_REG);