pkarashchenko commented on code in PR #9761: URL: https://github.com/apache/nuttx/pull/9761#discussion_r1258074515
########## arch/risc-v/src/hpm6000/hardware/hpm_gpio.h: ########## @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_GPIO_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include "hardware/hpm_memorymap.h" + +#if defined(CONFIG_ARCH_CHIP_HPM6360IPA) +#include "hpm6300/hpm6300_ioc.h" +#include "hpm6300/hpm6300_pinmux.h" +#else +#error The selected HPM variant is not impelemented +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIOA 0 +#define GPIOB 1 +#define GPIOC 2 +#define GPIOD 3 +#define GPIOE 4 +#define GPIOF 5 +#define GPIOX 6 +#define GPIOY 7 +#define GPIOZ 8 +#define HPM_GPIO_NPINS 32 + +/* Most registers are laid out simply with one bit per pin */ + +#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */ + +/* Register offsets *********************************************************/ + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H */ Review Comment: ```suggestion #endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H */ ``` ########## arch/risc-v/src/hpm6000/hardware/hpm_ioc.h: ########## @@ -0,0 +1,160 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_ioc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "hpm_ioc.h" + +#define CONFIG_ARCH_FAMILY_HPM6300 + +#if defined (CONFIG_ARCH_FAMILY_HPM6300) +# include "hardware/hpm6300/hpm6300_ioc.h" +#else +# error Unrecognized HPM chip +#endif + +#define DRIVE_260OHM (1) +#define DRIVE_130OHM (2) +#define DRIVE_88OHM (3) +#define DRIVE_65OHM (4) +#define DRIVE_52OHM (5) +#define DRIVE_43OHM (6) +#define DRIVE_37OHM (7) + +#define SPEED_SLOW (0) +#define SPEED_MEDIUM (1) +#define SPEED_FAST (2) +#define SPEED_MAX (3) + +#define PULL_DOWN_100K (0) +#define PULL_UP_100K (1) +#define PULL_UP_47K (2) +#define PULL_UP_22K (3) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pad Alt Registers */ + +#define IOC_PAD_FUNC_ALT_SELECT_SHIFT (0) +#define IOC_PAD_FUNC_ALT_SELECT_MASK (1f << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT(n) ((uint32_t)(n) << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT0 (0 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT1 (1 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT2 (2 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT3 (3 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT4 (4 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT5 (5 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT6 (6 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT7 (7 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT8 (8 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT9 (9 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT10 (10 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT11 (11 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT12 (12 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT13 (13 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT14 (14 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT15 (15 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT16 (16 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT17 (17 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT18 (18 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT19 (19 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT20 (20 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT21 (21 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT22 (22 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT23 (23 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT24 (24 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT25 (25 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT26 (26 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT27 (27 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT28 (28 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT29 (29 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT30 (30 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT31 (31 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) + +/* Pad Analog Registers */ + +#define IOC_PAD_FUNC_ANALOG (1 << 8) + +/* Pad Loop Back Registers */ + +#define IOC_PAD_FUNC_LOOP_BACK (1 << 16) + +/* Pad Drive strength Registers */ + +#define IOC_PAD_PAD_DS_SHIFT (0) +#define IOC_PAD_PAD_DS_MASK (0x7 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS(n) ((uint32_t)(n) << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_260OHM (1 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_130OHM (2 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_88OHM (3 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_65OHM (4 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_52OHM (5 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_43OHM (6 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_37OHM (7 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_157OHM (1 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_78OHM (2 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_53OHM (3 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_39OHM (4 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_32OHM (5 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_26OHM (6 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_23OHM (7 << IOC_PAD_PAD_DS_SHIFT) + +#define IOC_PAD_PAD_SPD_SHIFT (4) +#define IOC_PAD_PAD_SPD_MASK (0x3 << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD(n) ((uint32_t)(n) << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD_SLOW (0 << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD_MEDIUM (1 << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD_FAST (2 << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD_MAX (3 << IOC_PAD_PAD_SPD_SHIFT) + +#define IOC_PAD_PAD_SR (1 << 6) +#define IOC_PAD_PAD_OD (1 << 8) +#define IOC_PAD_PAD_KE (1 << 16) +#define IOC_PAD_PAD_PE (1 << 17) +#define IOC_PAD_PAD_PS (1 << 18) + +#define IOC_PAD_PAD_PRS_SHIFT (20) /* Bit 20-21: Pull up/down internal resistance strength */ +#define IOC_PAD_PAD_PRS_MASK (0x3 << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS(n) ((uint32_t)(n) << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS_DOWN_100K (0 << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS_UP_100K (0 << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS_UP_47K (1 << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS_UP_22K (2 << IOC_PAD_PAD_PRS_SHIFT) + +#define IOC_PAD_PAD_HYS (1 << 24) /* Bit 24: Schmitt Trigger Enable Field */ + +/* Defaults for drive conditions for each set of pins. These are a good + * starting point but should be updated once you've got real hardware + * to measure. + */ + +#define IOC_PAD_UART_DEFAULT (PAD_PULL_UP_22K | PAD_DRIVE_43OHM | \ + PAD_SLEW_SLOW | PAD_SPEED_SLOW | PAD_SCHMITT_TRIGGER) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H */ Review Comment: ```suggestion #endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H */ ``` ########## arch/risc-v/src/hpm6000/hpm_clockconfig.h: ########## @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_CLOCKCONFIG_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hpm_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CPU_DIV 1 +#define AXI_SUB_DIV 3 +#define AHB_SUB_DIV 3 +#define PLL1_DIV 1 +#define PLL1_FREQ 576000000 +#define AUD_DIV 46 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/** + * @brief Clock nodes + */ + +typedef enum +{ + clock_node_mchtmr0 = 0, + clock_node_femc = 1, + clock_node_xpi0 = 2, + clock_node_xpi1 = 3, Review Comment: 2 spaces ########## arch/risc-v/include/hpm6000/hpm_irq.h: ########## @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/risc-v/include/hpm6000/hpm_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H +#define __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Map RISC-V exception code to NuttX IRQ */ + +#define HPM_IRQ_PERI_START (RISCV_IRQ_ASYNC + 20) + +/* Machine Global External Interrupt */ + +#define HPM_IRQ_GPIO0_A (HPM_IRQ_PERI_START + 1) +#define HPM_IRQ_GPIO0_B (HPM_IRQ_PERI_START + 2) +#define HPM_IRQ_GPIO0_C (HPM_IRQ_PERI_START + 3) +#define HPM_IRQ_GPIO0_D (HPM_IRQ_PERI_START + 4) +#define HPM_IRQ_GPIO0_X (HPM_IRQ_PERI_START + 5) +#define HPM_IRQ_GPIO0_Y (HPM_IRQ_PERI_START + 6) +#define HPM_IRQ_GPIO0_Z (HPM_IRQ_PERI_START + 7) +#define HPM_IRQ_ADC0 (HPM_IRQ_PERI_START + 8) +#define HPM_IRQ_ADC1 (HPM_IRQ_PERI_START + 9) +#define HPM_IRQ_ADC2 (HPM_IRQ_PERI_START + 10) +#define HPM_IRQ_DAC (HPM_IRQ_PERI_START + 11) +#define HPM_IRQ_ACMP0 (HPM_IRQ_PERI_START + 12) +#define HPM_IRQ_ACMP1 (HPM_IRQ_PERI_START + 13) +#define HPM_IRQ_SPI0 (HPM_IRQ_PERI_START + 14) +#define HPM_IRQ_SPI1 (HPM_IRQ_PERI_START + 15) +#define HPM_IRQ_SPI2 (HPM_IRQ_PERI_START + 16) +#define HPM_IRQ_SPI3 (HPM_IRQ_PERI_START + 17) +#define HPM_IRQ_UART0 (HPM_IRQ_PERI_START + 18) +#define HPM_IRQ_UART1 (HPM_IRQ_PERI_START + 19) +#define HPM_IRQ_UART2 (HPM_IRQ_PERI_START + 20) +#define HPM_IRQ_UART3 (HPM_IRQ_PERI_START + 21) +#define HPM_IRQ_UART4 (HPM_IRQ_PERI_START + 22) +#define HPM_IRQ_UART5 (HPM_IRQ_PERI_START + 23) +#define HPM_IRQ_UART6 (HPM_IRQ_PERI_START + 24) +#define HPM_IRQ_UART7 (HPM_IRQ_PERI_START + 25) +#define HPM_IRQ_CAN0 (HPM_IRQ_PERI_START + 26) +#define HPM_IRQ_CAN1 (HPM_IRQ_PERI_START + 27) +#define HPM_IRQ_PTPC (HPM_IRQ_PERI_START + 28) +#define HPM_IRQ_WDG0 (HPM_IRQ_PERI_START + 29) +#define HPM_IRQ_WDG1 (HPM_IRQ_PERI_START + 30) +#define HPM_IRQ_TSNS (HPM_IRQ_PERI_START + 31) +#define HPM_IRQ_MBX0A (HPM_IRQ_PERI_START + 32) +#define HPM_IRQ_MBX0B (HPM_IRQ_PERI_START + 33) +#define HPM_IRQ_GPTMR0 (HPM_IRQ_PERI_START + 34) +#define HPM_IRQ_GPTMR1 (HPM_IRQ_PERI_START + 35) +#define HPM_IRQ_GPTMR2 (HPM_IRQ_PERI_START + 36) +#define HPM_IRQ_GPTMR3 (HPM_IRQ_PERI_START + 37) +#define HPM_IRQ_I2C0 (HPM_IRQ_PERI_START + 38) +#define HPM_IRQ_I2C1 (HPM_IRQ_PERI_START + 39) +#define HPM_IRQ_I2C2 (HPM_IRQ_PERI_START + 40) +#define HPM_IRQ_I2C3 (HPM_IRQ_PERI_START + 41) +#define HPM_IRQ_PWM0 (HPM_IRQ_PERI_START + 42) +#define HPM_IRQ_HALL0 (HPM_IRQ_PERI_START + 43) +#define HPM_IRQ_QEI0 (HPM_IRQ_PERI_START + 44) Review Comment: Please align all the block of defines ########## arch/risc-v/src/hpm6000/hpm.h: ########## @@ -0,0 +1,37 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6750_HPM6750_H +#define __ARCH_RISCV_SRC_HPM6750_HPM6750_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include <sys/types.h> +#include <stdint.h> +#include <stdbool.h> + +#include <arch/irq.h> +#include "riscv_internal.h" +#include "chip.h" + +#endif /* __ARCH_RISCV_SRC_HPM6750_HPM6750_H */ Review Comment: ```suggestion #endif /* __ARCH_RISCV_SRC_HPM6000_HPM6750_H */ ``` here and other similar places ########## arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h: ########## @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> +#include "hpm_ioc.h" +#include "hpm_gpio.h" + +#define GPIO_UART0_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA30_INDEX)) +#define GPIO_UART0_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB22_INDEX)) +#define GPIO_UART0_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC22_INDEX)) +#define GPIO_UART0_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY06_INDEX)) + +#define GPIO_UART0_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA31_INDEX)) +#define GPIO_UART0_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB23_INDEX)) +#define GPIO_UART0_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC23_INDEX)) +#define GPIO_UART0_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY07_INDEX)) + +#define GPIO_UART1_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA00_INDEX)) +#define GPIO_UART1_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB00_INDEX)) +#define GPIO_UART1_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB24_INDEX)) +#define GPIO_UART1_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC24_INDEX)) + +#define GPIO_UART1_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA01_INDEX)) +#define GPIO_UART1_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB01_INDEX)) +#define GPIO_UART1_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB25_INDEX)) +#define GPIO_UART1_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC25_INDEX)) + +#define GPIO_UART2_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA02_INDEX)) +#define GPIO_UART2_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB02_INDEX)) +#define GPIO_UART2_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB26_INDEX)) +#define GPIO_UART2_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC26_INDEX)) + +#define GPIO_UART2_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA03_INDEX)) +#define GPIO_UART2_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB03_INDEX)) +#define GPIO_UART2_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB27_INDEX)) +#define GPIO_UART2_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC27_INDEX)) + +#define GPIO_UART3_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA04_INDEX)) +#define GPIO_UART3_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB04_INDEX)) +#define GPIO_UART3_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB28_INDEX)) +#define GPIO_UART3_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ00_INDEX)) + +#define GPIO_UART3_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA05_INDEX)) +#define GPIO_UART3_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB05_INDEX)) +#define GPIO_UART3_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB28_INDEX)) +#define GPIO_UART3_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ01_INDEX)) + +#define GPIO_UART4_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA14_INDEX)) +#define GPIO_UART4_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB06_INDEX)) +#define GPIO_UART4_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC06_INDEX)) +#define GPIO_UART4_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ02_INDEX)) + +#define GPIO_UART4_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA15_INDEX)) +#define GPIO_UART4_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB07_INDEX)) +#define GPIO_UART4_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC07_INDEX)) +#define GPIO_UART4_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ03_INDEX)) + +#define GPIO_UART5_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA16_INDEX)) +#define GPIO_UART5_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB08_INDEX)) +#define GPIO_UART5_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC08_INDEX)) +#define GPIO_UART5_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ04_INDEX)) + +#define GPIO_UART5_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA17_INDEX)) +#define GPIO_UART5_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB09_INDEX)) +#define GPIO_UART5_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC09_INDEX)) +#define GPIO_UART5_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ05_INDEX)) + +#define GPIO_UART6_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA18_INDEX)) +#define GPIO_UART6_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB10_INDEX)) +#define GPIO_UART6_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC10_INDEX)) +#define GPIO_UART6_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ06_INDEX)) + +#define GPIO_UART6_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA19_INDEX)) +#define GPIO_UART6_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB11_INDEX)) +#define GPIO_UART6_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC11_INDEX)) +#define GPIO_UART6_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ07_INDEX)) + +#define GPIO_UART7_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA20_INDEX)) +#define GPIO_UART7_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB12_INDEX)) +#define GPIO_UART7_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC12_INDEX)) +#define GPIO_UART7_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY04_INDEX)) + +#define GPIO_UART7_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA21_INDEX)) +#define GPIO_UART7_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB13_INDEX)) +#define GPIO_UART7_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC13_INDEX)) +#define GPIO_UART7_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY05_INDEX)) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H */ Review Comment: ```suggestion #endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H */ ``` ########## arch/risc-v/include/hpm6000/hpm_irq.h: ########## @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/risc-v/include/hpm6000/hpm_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H +#define __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Map RISC-V exception code to NuttX IRQ */ + +#define HPM_IRQ_PERI_START (RISCV_IRQ_ASYNC + 20) + +/* Machine Global External Interrupt */ + +#define HPM_IRQ_GPIO0_A (HPM_IRQ_PERI_START + 1) +#define HPM_IRQ_GPIO0_B (HPM_IRQ_PERI_START + 2) +#define HPM_IRQ_GPIO0_C (HPM_IRQ_PERI_START + 3) +#define HPM_IRQ_GPIO0_D (HPM_IRQ_PERI_START + 4) +#define HPM_IRQ_GPIO0_X (HPM_IRQ_PERI_START + 5) +#define HPM_IRQ_GPIO0_Y (HPM_IRQ_PERI_START + 6) +#define HPM_IRQ_GPIO0_Z (HPM_IRQ_PERI_START + 7) +#define HPM_IRQ_ADC0 (HPM_IRQ_PERI_START + 8) +#define HPM_IRQ_ADC1 (HPM_IRQ_PERI_START + 9) +#define HPM_IRQ_ADC2 (HPM_IRQ_PERI_START + 10) +#define HPM_IRQ_DAC (HPM_IRQ_PERI_START + 11) +#define HPM_IRQ_ACMP0 (HPM_IRQ_PERI_START + 12) +#define HPM_IRQ_ACMP1 (HPM_IRQ_PERI_START + 13) +#define HPM_IRQ_SPI0 (HPM_IRQ_PERI_START + 14) +#define HPM_IRQ_SPI1 (HPM_IRQ_PERI_START + 15) +#define HPM_IRQ_SPI2 (HPM_IRQ_PERI_START + 16) +#define HPM_IRQ_SPI3 (HPM_IRQ_PERI_START + 17) +#define HPM_IRQ_UART0 (HPM_IRQ_PERI_START + 18) +#define HPM_IRQ_UART1 (HPM_IRQ_PERI_START + 19) +#define HPM_IRQ_UART2 (HPM_IRQ_PERI_START + 20) +#define HPM_IRQ_UART3 (HPM_IRQ_PERI_START + 21) +#define HPM_IRQ_UART4 (HPM_IRQ_PERI_START + 22) +#define HPM_IRQ_UART5 (HPM_IRQ_PERI_START + 23) +#define HPM_IRQ_UART6 (HPM_IRQ_PERI_START + 24) +#define HPM_IRQ_UART7 (HPM_IRQ_PERI_START + 25) +#define HPM_IRQ_CAN0 (HPM_IRQ_PERI_START + 26) +#define HPM_IRQ_CAN1 (HPM_IRQ_PERI_START + 27) +#define HPM_IRQ_PTPC (HPM_IRQ_PERI_START + 28) +#define HPM_IRQ_WDG0 (HPM_IRQ_PERI_START + 29) +#define HPM_IRQ_WDG1 (HPM_IRQ_PERI_START + 30) +#define HPM_IRQ_TSNS (HPM_IRQ_PERI_START + 31) +#define HPM_IRQ_MBX0A (HPM_IRQ_PERI_START + 32) +#define HPM_IRQ_MBX0B (HPM_IRQ_PERI_START + 33) +#define HPM_IRQ_GPTMR0 (HPM_IRQ_PERI_START + 34) +#define HPM_IRQ_GPTMR1 (HPM_IRQ_PERI_START + 35) +#define HPM_IRQ_GPTMR2 (HPM_IRQ_PERI_START + 36) +#define HPM_IRQ_GPTMR3 (HPM_IRQ_PERI_START + 37) +#define HPM_IRQ_I2C0 (HPM_IRQ_PERI_START + 38) +#define HPM_IRQ_I2C1 (HPM_IRQ_PERI_START + 39) +#define HPM_IRQ_I2C2 (HPM_IRQ_PERI_START + 40) +#define HPM_IRQ_I2C3 (HPM_IRQ_PERI_START + 41) +#define HPM_IRQ_PWM0 (HPM_IRQ_PERI_START + 42) +#define HPM_IRQ_HALL0 (HPM_IRQ_PERI_START + 43) +#define HPM_IRQ_QEI0 (HPM_IRQ_PERI_START + 44) +#define HPM_IRQ_PWM1 (HPM_IRQ_PERI_START + 45) +#define HPM_IRQ_HALL1 (HPM_IRQ_PERI_START + 46) +#define HPM_IRQ_QEI1 (HPM_IRQ_PERI_START + 47) +#define HPM_IRQ_SDP (HPM_IRQ_PERI_START + 48) +#define HPM_IRQ_XPI0 (HPM_IRQ_PERI_START + 49) +#define HPM_IRQ_XPI1 (HPM_IRQ_PERI_START + 50) +#define HPM_IRQ_XDMA (HPM_IRQ_PERI_START + 51) +#define HPM_IRQ_HDMA (HPM_IRQ_PERI_START + 52) +#define HPM_IRQ_FEMC (HPM_IRQ_PERI_START + 53) +#define HPM_IRQ_RNG (HPM_IRQ_PERI_START + 54) +#define HPM_IRQ_I2S0 (HPM_IRQ_PERI_START + 55) +#define HPM_IRQ_I2S1 (HPM_IRQ_PERI_START + 56) +#define HPM_IRQ_DAO (HPM_IRQ_PERI_START + 57) +#define HPM_IRQ_PDM (HPM_IRQ_PERI_START + 58) +#define HPM_IRQ_EFA (HPM_IRQ_PERI_START + 59) +#define HPM_IRQ_NTMR0 (HPM_IRQ_PERI_START + 60) +#define HPM_IRQ_USB0 (HPM_IRQ_PERI_START + 61) +#define HPM_IRQ_ENET0 (HPM_IRQ_PERI_START + 62) +#define HPM_IRQ_SDXC0 (HPM_IRQ_PERI_START + 63) +#define HPM_IRQ_PSEC (HPM_IRQ_PERI_START + 64) +#define HPM_IRQ_PGPIO (HPM_IRQ_PERI_START + 65) +#define HPM_IRQ_PWDG (HPM_IRQ_PERI_START + 66) +#define HPM_IRQ_PTMR (HPM_IRQ_PERI_START + 67) +#define HPM_IRQ_PUART (HPM_IRQ_PERI_START + 68) +#define HPM_IRQ_FUSE (HPM_IRQ_PERI_START + 69) +#define HPM_IRQ_SECMON (HPM_IRQ_PERI_START + 70) +#define HPM_IRQ_RTC (HPM_IRQ_PERI_START + 71) +#define HPM_IRQ_BUTN (HPM_IRQ_PERI_START + 72) +#define HPM_IRQ_BGPIO (HPM_IRQ_PERI_START + 73) +#define HPM_IRQ_BVIO (HPM_IRQ_PERI_START + 74) +#define HPM_IRQ_BROWNOUT (HPM_IRQ_PERI_START + 75) +#define HPM_IRQ_SYSCTL (HPM_IRQ_PERI_START + 76) + +/* Total number of IRQs */ + +#define NR_IRQS (HPM_IRQ_PERI_START + 76) + +#endif /* __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H */ Review Comment: ```suggestion #endif /* __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H */ ``` ########## arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h: ########## @@ -0,0 +1,693 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hpm6300_memorymap.h" + +#define HPM_SYSCTL_RESOURCE_CPU0 (HPM_SYSCTL_BASE + 0x0000) +#define HPM_SYSCTL_RESOURCE_CPX0 (HPM_SYSCTL_BASE + 0x0004) +#define HPM_SYSCTL_RESOURCE_POW_CPU0 (HPM_SYSCTL_BASE + 0x0054) +#define HPM_SYSCTL_RESOURCE_RST_SOC (HPM_SYSCTL_BASE + 0x0058) +#define HPM_SYSCTL_RESOURCE_RST_CPU0 (HPM_SYSCTL_BASE + 0x005c) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_XTAL (HPM_SYSCTL_BASE + 0x0080) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL0 (HPM_SYSCTL_BASE + 0x0084) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (HPM_SYSCTL_BASE + 0x0088) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (HPM_SYSCTL_BASE + 0x008c) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (HPM_SYSCTL_BASE + 0x0090) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL1 (HPM_SYSCTL_BASE + 0x0094) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (HPM_SYSCTL_BASE + 0x0098) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (HPM_SYSCTL_BASE + 0x009c) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL2 (HPM_SYSCTL_BASE + 0x00a0) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (HPM_SYSCTL_BASE + 0x00a4) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (HPM_SYSCTL_BASE + 0x00a8) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (HPM_SYSCTL_BASE + 0x00ac) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (HPM_SYSCTL_BASE + 0x00b0) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (HPM_SYSCTL_BASE + 0x00b4) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_CPU0 (HPM_SYSCTL_BASE + 0x0100) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_MCT0 (HPM_SYSCTL_BASE + 0x0104) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_FEMC (HPM_SYSCTL_BASE + 0x0108) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_XPI0 (HPM_SYSCTL_BASE + 0x010c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_XPI1 (HPM_SYSCTL_BASE + 0x0110) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR0 (HPM_SYSCTL_BASE + 0x0114) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR1 (HPM_SYSCTL_BASE + 0x0118) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR2 (HPM_SYSCTL_BASE + 0x011c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR3 (HPM_SYSCTL_BASE + 0x0120) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART0 (HPM_SYSCTL_BASE + 0x0124) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART1 (HPM_SYSCTL_BASE + 0x0128) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART2 (HPM_SYSCTL_BASE + 0x012c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART3 (HPM_SYSCTL_BASE + 0x0130) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART4 (HPM_SYSCTL_BASE + 0x0134) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART5 (HPM_SYSCTL_BASE + 0x0138) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART6 (HPM_SYSCTL_BASE + 0x013c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART7 (HPM_SYSCTL_BASE + 0x0140) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2C0 (HPM_SYSCTL_BASE + 0x0144) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC21 (HPM_SYSCTL_BASE + 0x0148) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC22 (HPM_SYSCTL_BASE + 0x014c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC23 (HPM_SYSCTL_BASE + 0x0150) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI0 (HPM_SYSCTL_BASE + 0x0154) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI1 (HPM_SYSCTL_BASE + 0x0158) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI2 (HPM_SYSCTL_BASE + 0x015c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI3 (HPM_SYSCTL_BASE + 0x0160) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_CAN0 (HPM_SYSCTL_BASE + 0x0164) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_CAN1 (HPM_SYSCTL_BASE + 0x0168) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_PTPC (HPM_SYSCTL_BASE + 0x016c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA0 (HPM_SYSCTL_BASE + 0x0170) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA1 (HPM_SYSCTL_BASE + 0x0174) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA2 (HPM_SYSCTL_BASE + 0x0178) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA3 (HPM_SYSCTL_BASE + 0x017c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_AUD0 (HPM_SYSCTL_BASE + 0x0180) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_AUD1 (HPM_SYSCTL_BASE + 0x0184) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ETH0 (HPM_SYSCTL_BASE + 0x0188) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_PTP0 (HPM_SYSCTL_BASE + 0x018c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_REF0 (HPM_SYSCTL_BASE + 0x0190) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_REF1 (HPM_SYSCTL_BASE + 0x0194) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_NTM0 (HPM_SYSCTL_BASE + 0x0198) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SDC0 (HPM_SYSCTL_BASE + 0x019c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC0 (HPM_SYSCTL_BASE + 0x0200) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC1 (HPM_SYSCTL_BASE + 0x0204) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC2 (HPM_SYSCTL_BASE + 0x0208) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_DAC0 (HPM_SYSCTL_BASE + 0x020c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2S0 (HPM_SYSCTL_BASE + 0x0210) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2S1 (HPM_SYSCTL_BASE + 0x0214) +#define HPM_SYSCTL_RESOURCE_AHBP (HPM_SYSCTL_BASE + 0x0400) +#define HPM_SYSCTL_RESOURCE_AXIS (HPM_SYSCTL_BASE + 0x0404) +#define HPM_SYSCTL_RESOURCE_AXIC (HPM_SYSCTL_BASE + 0x0408) +#define HPM_SYSCTL_RESOURCE_FEMC (HPM_SYSCTL_BASE + 0x040c) +#define HPM_SYSCTL_RESOURCE_ROM0 (HPM_SYSCTL_BASE + 0x0410) +#define HPM_SYSCTL_RESOURCE_LMM0 (HPM_SYSCTL_BASE + 0x0414) +#define HPM_SYSCTL_RESOURCE_RAM0 (HPM_SYSCTL_BASE + 0x0418) +#define HPM_SYSCTL_RESOURCE_MCT0 (HPM_SYSCTL_BASE + 0x041c) +#define HPM_SYSCTL_RESOURCE_XPI0 (HPM_SYSCTL_BASE + 0x0420) +#define HPM_SYSCTL_RESOURCE_XPI1 (HPM_SYSCTL_BASE + 0x0424) +#define HPM_SYSCTL_RESOURCE_SDP0 (HPM_SYSCTL_BASE + 0x0428) +#define HPM_SYSCTL_RESOURCE_RNG0 (HPM_SYSCTL_BASE + 0x042c) +#define HPM_SYSCTL_RESOURCE_KMAN (HPM_SYSCTL_BASE + 0x0430) +#define HPM_SYSCTL_RESOURCE_DMA0 (HPM_SYSCTL_BASE + 0x0434) +#define HPM_SYSCTL_RESOURCE_DMA1 (HPM_SYSCTL_BASE + 0x0438) +#define HPM_SYSCTL_RESOURCE_FFA0 (HPM_SYSCTL_BASE + 0x043c) +#define HPM_SYSCTL_RESOURCE_GPIO (HPM_SYSCTL_BASE + 0x0440) +#define HPM_SYSCTL_RESOURCE_MBX0 (HPM_SYSCTL_BASE + 0x0444) +#define HPM_SYSCTL_RESOURCE_WDG0 (HPM_SYSCTL_BASE + 0x0448) +#define HPM_SYSCTL_RESOURCE_WDG1 (HPM_SYSCTL_BASE + 0x044c) +#define HPM_SYSCTL_RESOURCE_TSNS (HPM_SYSCTL_BASE + 0x0450) +#define HPM_SYSCTL_RESOURCE_TMR0 (HPM_SYSCTL_BASE + 0x0454) +#define HPM_SYSCTL_RESOURCE_TMR1 (HPM_SYSCTL_BASE + 0x0458) +#define HPM_SYSCTL_RESOURCE_RMR2 (HPM_SYSCTL_BASE + 0x045c) +#define HPM_SYSCTL_RESOURCE_TMR3 (HPM_SYSCTL_BASE + 0x0460) +#define HPM_SYSCTL_RESOURCE_URT0 (HPM_SYSCTL_BASE + 0x0464) +#define HPM_SYSCTL_RESOURCE_URT1 (HPM_SYSCTL_BASE + 0x0468) +#define HPM_SYSCTL_RESOURCE_URT2 (HPM_SYSCTL_BASE + 0x046c) +#define HPM_SYSCTL_RESOURCE_URT3 (HPM_SYSCTL_BASE + 0x0470) +#define HPM_SYSCTL_RESOURCE_URT4 (HPM_SYSCTL_BASE + 0x0474) +#define HPM_SYSCTL_RESOURCE_URT5 (HPM_SYSCTL_BASE + 0x0478) +#define HPM_SYSCTL_RESOURCE_URT6 (HPM_SYSCTL_BASE + 0x047c) +#define HPM_SYSCTL_RESOURCE_URT7 (HPM_SYSCTL_BASE + 0x0480) +#define HPM_SYSCTL_RESOURCE_I2C0 (HPM_SYSCTL_BASE + 0x0484) +#define HPM_SYSCTL_RESOURCE_I2C1 (HPM_SYSCTL_BASE + 0x0488) +#define HPM_SYSCTL_RESOURCE_I2C2 (HPM_SYSCTL_BASE + 0x048c) +#define HPM_SYSCTL_RESOURCE_I2C3 (HPM_SYSCTL_BASE + 0x0490) +#define HPM_SYSCTL_RESOURCE_SPI0 (HPM_SYSCTL_BASE + 0x0494) +#define HPM_SYSCTL_RESOURCE_SPI1 (HPM_SYSCTL_BASE + 0x0498) +#define HPM_SYSCTL_RESOURCE_SPI2 (HPM_SYSCTL_BASE + 0x049c) +#define HPM_SYSCTL_RESOURCE_SPI3 (HPM_SYSCTL_BASE + 0x04a0) +#define HPM_SYSCTL_RESOURCE_CAN0 (HPM_SYSCTL_BASE + 0x04a4) +#define HPM_SYSCTL_RESOURCE_CAN1 (HPM_SYSCTL_BASE + 0x04a8) +#define HPM_SYSCTL_RESOURCE_PTPC (HPM_SYSCTL_BASE + 0x04ac) +#define HPM_SYSCTL_RESOURCE_ADC0 (HPM_SYSCTL_BASE + 0x04b0) +#define HPM_SYSCTL_RESOURCE_ADC1 (HPM_SYSCTL_BASE + 0x04b4) +#define HPM_SYSCTL_RESOURCE_ADC2 (HPM_SYSCTL_BASE + 0x04b8) +#define HPM_SYSCTL_RESOURCE_DAC0 (HPM_SYSCTL_BASE + 0x04bc) +#define HPM_SYSCTL_RESOURCE_ACMP (HPM_SYSCTL_BASE + 0x04c0) +#define HPM_SYSCTL_RESOURCE_I2S0 (HPM_SYSCTL_BASE + 0x04c4) +#define HPM_SYSCTL_RESOURCE_I2S1 (HPM_SYSCTL_BASE + 0x04c8) +#define HPM_SYSCTL_RESOURCE_PDM0 (HPM_SYSCTL_BASE + 0x04cc) +#define HPM_SYSCTL_RESOURCE_DAO (HPM_SYSCTL_BASE + 0x04d0) +#define HPM_SYSCTL_RESOURCE_MSYN (HPM_SYSCTL_BASE + 0x04d4) +#define HPM_SYSCTL_RESOURCE_MOT0 (HPM_SYSCTL_BASE + 0x04d8) +#define HPM_SYSCTL_RESOURCE_MOT1 (HPM_SYSCTL_BASE + 0x04dc) +#define HPM_SYSCTL_RESOURCE_ETH0 (HPM_SYSCTL_BASE + 0x04e0) +#define HPM_SYSCTL_RESOURCE_NTM0 (HPM_SYSCTL_BASE + 0x04e4) +#define HPM_SYSCTL_RESOURCE_SDC0 (HPM_SYSCTL_BASE + 0x04e8) +#define HPM_SYSCTL_RESOURCE_USB0 (HPM_SYSCTL_BASE + 0x04ec) +#define HPM_SYSCTL_RESOURCE_REF0 (HPM_SYSCTL_BASE + 0x04f0) +#define HPM_SYSCTL_RESOURCE_REF1 (HPM_SYSCTL_BASE + 0x04f4) +#define HPM_SYSCTL_GROUP0_LINK0_VALUE (HPM_SYSCTL_BASE + 0x0800) +#define HPM_SYSCTL_GROUP0_LINK0_SET (HPM_SYSCTL_BASE + 0x0804) +#define HPM_SYSCTL_GROUP0_LINK0_CLEAR (HPM_SYSCTL_BASE + 0x0808) +#define HPM_SYSCTL_GROUP0_LINK0_TOGGLE (HPM_SYSCTL_BASE + 0x080c) +#define HPM_SYSCTL_GROUP0_LINK1_VALUE (HPM_SYSCTL_BASE + 0x0810) +#define HPM_SYSCTL_GROUP0_LINK1_SET (HPM_SYSCTL_BASE + 0x0814) +#define HPM_SYSCTL_GROUP0_LINK1_CLEAR (HPM_SYSCTL_BASE + 0x0818) +#define HPM_SYSCTL_GROUP0_LINK1_TOGGLE (HPM_SYSCTL_BASE + 0x081c) +#define HPM_SYSCTL_AFFILIATE_CPU0_VALUE (HPM_SYSCTL_BASE + 0x0900) +#define HPM_SYSCTL_AFFILIATE_CPU0_SET (HPM_SYSCTL_BASE + 0x0904) +#define HPM_SYSCTL_AFFILIATE_CPU0_CLEAR (HPM_SYSCTL_BASE + 0x0908) +#define HPM_SYSCTL_AFFILIATE_CPU0_TOGGLE (HPM_SYSCTL_BASE + 0x090c) +#define HPM_SYSCTL_RETENTION_CPU0_VALUE (HPM_SYSCTL_BASE + 0x0920) +#define HPM_SYSCTL_RETENTION_CPU0_SET (HPM_SYSCTL_BASE + 0x0924) +#define HPM_SYSCTL_RETENTION_CPU0_CLEAR (HPM_SYSCTL_BASE + 0x0928) +#define HPM_SYSCTL_RETENTION_CPU0_TOGGLE (HPM_SYSCTL_BASE + 0x092c) +#define HPM_SYSCTL_POWER_CPU0_STATUS (HPM_SYSCTL_BASE + 0x1000) +#define HPM_SYSCTL_POWER_CPU0_LF_WAIT (HPM_SYSCTL_BASE + 0x1004) +#define HPM_SYSCTL_POWER_CPU0_OFF_WAIT (HPM_SYSCTL_BASE + 0x100c) +#define HPM_SYSCTL_RESET_SOC_CONTROL (HPM_SYSCTL_BASE + 0x1400) +#define HPM_SYSCTL_RESET_SOC_CONFIG (HPM_SYSCTL_BASE + 0x1404) +#define HPM_SYSCTL_RESET_SOC_COUNTER (HPM_SYSCTL_BASE + 0x140c) +#define HPM_SYSCTL_RESET_CPU0_CONTROL (HPM_SYSCTL_BASE + 0x1410) +#define HPM_SYSCTL_RESET_CPU0_CONFIG (HPM_SYSCTL_BASE + 0x1414) +#define HPM_SYSCTL_RESET_CPU0_COUNTER (HPM_SYSCTL_BASE + 0x141c) +#define HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (HPM_SYSCTL_BASE + 0x1800) +#define HPM_SYSCTL_CLOCK_CLK_TOP_MCT0 (HPM_SYSCTL_BASE + 0x1804) +#define HPM_SYSCTL_CLOCK_CLK_TOP_FEMC (HPM_SYSCTL_BASE + 0x1808) +#define HPM_SYSCTL_CLOCK_CLK_TOP_XPI0 (HPM_SYSCTL_BASE + 0x180c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_XPI1 (HPM_SYSCTL_BASE + 0x1810) +#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR0 (HPM_SYSCTL_BASE + 0x1814) +#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR1 (HPM_SYSCTL_BASE + 0x1818) +#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR2 (HPM_SYSCTL_BASE + 0x181c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR3 (HPM_SYSCTL_BASE + 0x1820) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART0 (HPM_SYSCTL_BASE + 0x1824) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART1 (HPM_SYSCTL_BASE + 0x1828) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART2 (HPM_SYSCTL_BASE + 0x182c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART3 (HPM_SYSCTL_BASE + 0x1830) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART4 (HPM_SYSCTL_BASE + 0x1834) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART5 (HPM_SYSCTL_BASE + 0x1838) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART6 (HPM_SYSCTL_BASE + 0x183c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART7 (HPM_SYSCTL_BASE + 0x1840) +#define HPM_SYSCTL_CLOCK_CLK_TOP_I2C0 (HPM_SYSCTL_BASE + 0x1844) +#define HPM_SYSCTL_CLOCK_CLK_TOP_IC21 (HPM_SYSCTL_BASE + 0x1848) +#define HPM_SYSCTL_CLOCK_CLK_TOP_IC22 (HPM_SYSCTL_BASE + 0x184c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_IC23 (HPM_SYSCTL_BASE + 0x1850) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI0 (HPM_SYSCTL_BASE + 0x1854) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI1 (HPM_SYSCTL_BASE + 0x1858) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI2 (HPM_SYSCTL_BASE + 0x185c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI3 (HPM_SYSCTL_BASE + 0x1860) +#define HPM_SYSCTL_CLOCK_CLK_TOP_CAN0 (HPM_SYSCTL_BASE + 0x1864) +#define HPM_SYSCTL_CLOCK_CLK_TOP_CAN1 (HPM_SYSCTL_BASE + 0x1868) +#define HPM_SYSCTL_CLOCK_CLK_TOP_PTPC (HPM_SYSCTL_BASE + 0x186c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA0 (HPM_SYSCTL_BASE + 0x1870) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA1 (HPM_SYSCTL_BASE + 0x1874) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA2 (HPM_SYSCTL_BASE + 0x1878) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA3 (HPM_SYSCTL_BASE + 0x187c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_AUD0 (HPM_SYSCTL_BASE + 0x1880) +#define HPM_SYSCTL_CLOCK_CLK_TOP_AUD1 (HPM_SYSCTL_BASE + 0x1884) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ETH0 (HPM_SYSCTL_BASE + 0x1888) +#define HPM_SYSCTL_CLOCK_CLK_TOP_PTP0 (HPM_SYSCTL_BASE + 0x188c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_REF0 (HPM_SYSCTL_BASE + 0x1890) +#define HPM_SYSCTL_CLOCK_CLK_TOP_REF1 (HPM_SYSCTL_BASE + 0x1894) +#define HPM_SYSCTL_CLOCK_CLK_TOP_NTM0 (HPM_SYSCTL_BASE + 0x1898) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SDC0 (HPM_SYSCTL_BASE + 0x189c) +#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC0 (HPM_SYSCTL_BASE + 0x1c00) +#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC1 (HPM_SYSCTL_BASE + 0x1c04) +#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC2 (HPM_SYSCTL_BASE + 0x1c08) +#define HPM_SYSCTL_ADCCLK_CLK_TOP_DAC0 (HPM_SYSCTL_BASE + 0x1c0c) +#define HPM_SYSCTL_I2SCLK_CLK_TOP_I2S0 (HPM_SYSCTL_BASE + 0x1c10) +#define HPM_SYSCTL_I2SCLK_CLK_TOP_I2S1 (HPM_SYSCTL_BASE + 0x1c14) +#define HPM_SYSCTL_GLOBAL00 (HPM_SYSCTL_BASE + 0x2000) +#define HPM_SYSCTL_MONITOR_SLICE0_CONTROL (HPM_SYSCTL_BASE + 0x2400) +#define HPM_SYSCTL_MONITOR_SLICE0_CURRENT (HPM_SYSCTL_BASE + 0x2404) +#define HPM_SYSCTL_MONITOR_SLICE0_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2408) +#define HPM_SYSCTL_MONITOR_SLICE0_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x240c) +#define HPM_SYSCTL_MONITOR_SLICE1_CONTROL (HPM_SYSCTL_BASE + 0x2420) +#define HPM_SYSCTL_MONITOR_SLICE1_CURRENT (HPM_SYSCTL_BASE + 0x2424) +#define HPM_SYSCTL_MONITOR_SLICE1_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2428) +#define HPM_SYSCTL_MONITOR_SLICE1_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x242c) +#define HPM_SYSCTL_MONITOR_SLICE2_CONTROL (HPM_SYSCTL_BASE + 0x2440) +#define HPM_SYSCTL_MONITOR_SLICE2_CURRENT (HPM_SYSCTL_BASE + 0x2444) +#define HPM_SYSCTL_MONITOR_SLICE2_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2448) +#define HPM_SYSCTL_MONITOR_SLICE2_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x244c) +#define HPM_SYSCTL_MONITOR_SLICE3_CONTROL (HPM_SYSCTL_BASE + 0x2460) +#define HPM_SYSCTL_MONITOR_SLICE3_CURRENT (HPM_SYSCTL_BASE + 0x2464) +#define HPM_SYSCTL_MONITOR_SLICE3_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2468) +#define HPM_SYSCTL_MONITOR_SLICE3_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x246c) +#define HPM_SYSCTL_CPU_CPU0_LP (HPM_SYSCTL_BASE + 0x2800) +#define HPM_SYSCTL_CPU_CPU0_LOCK (HPM_SYSCTL_BASE + 0x2804) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR0 (HPM_SYSCTL_BASE + 0x2808) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR1 (HPM_SYSCTL_BASE + 0x280c) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR2 (HPM_SYSCTL_BASE + 0x2810) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR3 (HPM_SYSCTL_BASE + 0x2814) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR4 (HPM_SYSCTL_BASE + 0x2818) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR5 (HPM_SYSCTL_BASE + 0x281c) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR6 (HPM_SYSCTL_BASE + 0x2820) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR7 (HPM_SYSCTL_BASE + 0x2824) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR8 (HPM_SYSCTL_BASE + 0x2828) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR9 (HPM_SYSCTL_BASE + 0x282c) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR10 (HPM_SYSCTL_BASE + 0x2830) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR11 (HPM_SYSCTL_BASE + 0x2834) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR12 (HPM_SYSCTL_BASE + 0x2838) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR13 (HPM_SYSCTL_BASE + 0x283c) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS0 (HPM_SYSCTL_BASE + 0x2840) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS1 (HPM_SYSCTL_BASE + 0x2844) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS2 (HPM_SYSCTL_BASE + 0x2848) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS3 (HPM_SYSCTL_BASE + 0x284c) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE0 (HPM_SYSCTL_BASE + 0x2880) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE1 (HPM_SYSCTL_BASE + 0x2884) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE2 (HPM_SYSCTL_BASE + 0x2888) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE3 (HPM_SYSCTL_BASE + 0x288c) + +#define SYSCTL_RESOURCE_GLB_BUSY (1 << 31) +#define SYSCTL_RESOURCE_LOC_BUSY (1 << 30) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_MASK (0x3U << SYSCTL_RESOURCE_MODE_SHIFT) +# define SYSCTL_RESOURCE_MODE_AUTO (0 << SYSCTL_RESOURCE_MODE_SHIFT) +# define SYSCTL_RESOURCE_MODE_ON (1 << SYSCTL_RESOURCE_MODE_SHIFT) +# define SYSCTL_RESOURCE_MODE_OFF (2 << SYSCTL_RESOURCE_MODE_SHIFT) +# define SYSCTL_RESOURCE_MODE_RESV (3 << SYSCTL_RESOURCE_MODE_SHIFT) + +#define SYSCTL_GROUP0(n) (1U << (n)) + +#define SYSCTL_AFFILIATE(n) (1U << (n)) + +#define SYSCTL_RETENTION_LINK_SHIFT (0) +#define SYSCTL_RETENTION_LINK_MASK (0xffU << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_SOC_RAM (0 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_PERIPH_REG (1 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_CPU0_RAM (2 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_CPU0_REG (3 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_XTAL (4 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_PLL0 (5 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_PLL1 (6 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_PLL2 (7 << SYSCTL_RETENTION_LINK_SHIFT) + +#define SYSCTL_POWER_STATUS_FLAG (1 << 31) +#define SYSCTL_POWER_STATUS_FLAG_WAKE (1 << 30) +#define SYSCTL_POWER_LF_DISABLE (1 << 12) +#define SYSCTL_POWER_LF_ACK (1 << 8) + +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0) +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xfffffU << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) +#define SYSCTL_POWER_LF_WAIT_WAIT(n) ((n) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0) +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xfffffU << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) +#define SYSCTL_POWER_OFF_WAIT_WAIT(n) ((n) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +#define SYSCTL_RESET_CONTROL_FLAG (1 << 31) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE (1 << 30) +#define SYSCTL_RESET_CONTROL_HOLD (1 << 4) +#define SYSCTL_RESET_CONTROL_RESET (1 << 0) + +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xffU << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) +#define SYSCTL_RESET_CONFIG_PRE_WAIT(n) ((n) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xffU << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM(n) ((n) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0) +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xffU << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) +#define SYSCTL_RESET_CONFIG_POST_WAIT(n) ((n) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0) +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xfffffU << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) +#define SYSCTL_RESET_COUNTER_COUNTER(n) ((n) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +#define SYSCTL_CLOCK_CPU_GLB_BUSY (1 << 31) +#define SYSCTL_CLOCK_CPU_LOC_BUSY (1 << 30) +#define SYSCTL_CLOCK_CPU_PRESERVE (1 << 28) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xfU << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_SUB1_DIV(n) ((n) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xfU << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_SUB0_DIV(n) ((n) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8) +#define SYSCTL_CLOCK_CPU_MUX_MASK (0xfU << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_OSC0_CLK0 (0 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK0 (1 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK1 (2 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK2 (3 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 (4 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL1_CLK1 (5 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL2_CLK0 (6 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL2_CLK1 (7 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0) +#define SYSCTL_CLOCK_CPU_DIV_MASK (0xffU << SYSCTL_CLOCK_CPU_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_DIV(n) ((n) << SYSCTL_CLOCK_CPU_DIV_SHIFT) + +#define SYSCTL_CLOCK_GLB_BUSY (1 << 31) +#define SYSCTL_CLOCK_LOC_BUSY (1 << 30) +#define SYSCTL_CLOCK_PRESERVE (1 << 28) +#define SYSCTL_CLOCK_SUB1_DIV_SHIFT (20) +#define SYSCTL_CLOCK_SUB1_DIV_MASK (0xfU << SYSCTL_CLOCK_SUB1_DIV_SHIFT) +#define SYSCTL_CLOCK_SUB1_DIV(n) ((n) << SYSCTL_CLOCK_SUB1_DIV_SHIFT) +#define SYSCTL_CLOCK_SUB0_DIV_SHIFT (16) +#define SYSCTL_CLOCK_SUB0_DIV_MASK (0xfU << SYSCTL_CLOCK_SUB0_DIV_SHIFT) +#define SYSCTL_CLOCK_SUB0_DIV(n) ((n) << SYSCTL_CLOCK_SUB0_DIV_SHIFT) +#define SYSCTL_CLOCK_MUX_SHIFT (8) +#define SYSCTL_CLOCK_MUX_MASK (0xfU << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_OSC0_CLK0 (0 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL0_CLK0 (1 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL0_CLK1 (2 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL0_CLK2 (3 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL1_CLK0 (4 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL1_CLK1 (5 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL2_CLK0 (6 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL2_CLK1 (7 << SYSCTL_CLOCK_MUX_SHIFT) +#define SYSCTL_CLOCK_DIV_SHIFT (0) +#define SYSCTL_CLOCK_DIV_MASK (0xffU << SYSCTL_CLOCK_DIV_SHIFT) +#define SYSCTL_CLOCK_DIV(n) ((n-1) << SYSCTL_CLOCK_DIV_SHIFT) + +#define SYSCTL_ADCCLK_GLB_BUSY (1 << 31) +#define SYSCTL_ADCCLK_LOC_BUSY (1 << 30) +#define SYSCTL_ADCCLK_PRESERVE (1 << 28) +#define SYSCTL_ADCCLK_MUX_ANA_CLOCK (0) +#define SYSCTL_ADCCLK_MUX_AHB_CLOCK (1 << 8) + +#define SYSCTL_DACCLK_GLB_BUSY (1 << 31) +#define SYSCTL_DACCLK_LOC_BUSY (1 << 30) +#define SYSCTL_DACCLK_PRESERVE (1 << 28) +#define SYSCTL_DACCLK_MUX_ANA_CLOCK (0) +#define SYSCTL_DACCLK_MUX_AHB_CLOCK (1 << 8) + +#define SYSCTL_DACCLK_GLB_BUSY (1 << 31) +#define SYSCTL_DACCLK_LOC_BUSY (1 << 30) +#define SYSCTL_DACCLK_PRESERVE (1 << 28) +#define SYSCTL_DACCLK_MUX_AUD_CLOCK0 (0) +#define SYSCTL_DACCLK_MUX_AUD_CLOCK1 (1 << 8) + +#define SYSCTL_GLOBAL00_MUX_SHIFT (0) +#define SYSCTL_GLOBAL00_MUX_MASK (3 << SYSCTL_GLOBAL00_MUX_SHIFT) +#define SYSCTL_GLOBAL00_MUX(n) ((n) << SYSCTL_GLOBAL00_MUX_SHIFT) +#define SYSCTL_GLOBAL00_MUX_24M (0) +#define SYSCTL_GLOBAL00_MUX_SUG (1 << 1) + +#define SYSCTL_MONITOR_CONTROL_VALID (1 << 31) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY (1 << 27) +#define SYSCTL_MONITOR_CONTROL_OUTEN (1 << 24) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16) +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xffU << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) +#define SYSCTL_MONITOR_CONTROL_DIV(n) ((n) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) +#define SYSCTL_MONITOR_CONTROL_HIGH (1 << 15) +#define SYSCTL_MONITOR_CONTROL_LOW (1 << 14) +#define SYSCTL_MONITOR_CONTROL_START (1 << 12) +#define SYSCTL_MONITOR_CONTROL_MODE (1 << 10) +#define SYSCTL_MONITOR_CONTROL_ACCURACY (1 << 9) +#define SYSCTL_MONITOR_CONTROL_REFERENCE (1 << 8) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0) +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xffU << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) +#define SYSCTL_MONITOR_CONTROL_SELECTION(n) ((n) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24) +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xffU << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) +#define SYSCTL_CPU_LP_WAKE_CNT_CLEAR (0) +#define SYSCTL_CPU_LP_HALT (1 << 16) +#define SYSCTL_CPU_LP_WAKE (1 << 13) +#define SYSCTL_CPU_LP_EXEC (1 << 12) +#define SYSCTL_CPU_LP_WAKE_FLAG (1 << 10) +#define SYSCTL_CPU_LP_SLEEP_FLAG (1 << 9) +#define SYSCTL_CPU_LP_RESET_FLAG (1 << 8) +#define SYSCTL_CPU_LP_MODE_SHIFT (0) +#define SYSCTL_CPU_LP_MODE_MASK (0x3 << SYSCTL_CPU_LP_MODE_SHIFT) +#define SYSCTL_CPU_LP_MODE_WAIT (0 << SYSCTL_CPU_LP_MODE_SHIFT) +#define SYSCTL_CPU_LP_MODE_HALT (1 << SYSCTL_CPU_LP_MODE_SHIFT) +#define SYSCTL_CPU_LP_MODE_RUN (2 << SYSCTL_CPU_LP_MODE_SHIFT) + +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2) +#define SYSCTL_CPU_LOCK_GPR_MASK (0x3f << SYSCTL_CPU_LOCK_GPR_SHIFT) +#define SYSCTL_CPU_LOCK_LOCK (1 << 1) + +#define SYSCTL_CPU_GPR_GPR_MASK (0xffff) + +#define SYSCTL_CPU_WAKEUP_STATUS_MASK (0xffff) + +#define SYSCTL_CPU_WAKEUP_ENABLE_MASK (0xffff) + +#define SYSCTL_GROUP0_LINK0_AHBP (1 << 0) +#define SYSCTL_GROUP0_LINK0_AXIS (1 << 1) +#define SYSCTL_GROUP0_LINK0_AXIC (1 << 2) +#define SYSCTL_GROUP0_LINK0_FEMC (1 << 3) +#define SYSCTL_GROUP0_LINK0_ROM0 (1 << 4) +#define SYSCTL_GROUP0_LINK0_LMM0 (1 << 5) +#define SYSCTL_GROUP0_LINK0_RAM0 (1 << 6) +#define SYSCTL_GROUP0_LINK0_MCHTMR0 (1 << 7) +#define SYSCTL_GROUP0_LINK0_XPI0 (1 << 8) +#define SYSCTL_GROUP0_LINK0_XPI1 (1 << 9) +#define SYSCTL_GROUP0_LINK0_SDP0 (1 << 10) +#define SYSCTL_GROUP0_LINK0_RNG0 (1 << 11) +#define SYSCTL_GROUP0_LINK0_KMAN (1 << 12) +#define SYSCTL_GROUP0_LINK0_DMA0 (1 << 13) +#define SYSCTL_GROUP0_LINK0_DMA1 (1 << 14) +#define SYSCTL_GROUP0_LINK0_FFA0 (1 << 15) +#define SYSCTL_GROUP0_LINK0_GPIO (1 << 16) +#define SYSCTL_GROUP0_LINK0_MBX0 (1 << 17) +#define SYSCTL_GROUP0_LINK0_WDG0 (1 << 18) +#define SYSCTL_GROUP0_LINK0_WDG1 (1 << 19) +#define SYSCTL_GROUP0_LINK0_TSNS (1 << 20) +#define SYSCTL_GROUP0_LINK0_GPTMR0 (1 << 21) +#define SYSCTL_GROUP0_LINK0_GPTMR1 (1 << 22) +#define SYSCTL_GROUP0_LINK0_GPRMR2 (1 << 23) +#define SYSCTL_GROUP0_LINK0_GPTMR3 (1 << 24) +#define SYSCTL_GROUP0_LINK0_UART0 (1 << 25) +#define SYSCTL_GROUP0_LINK0_UART1 (1 << 26) +#define SYSCTL_GROUP0_LINK0_UART2 (1 << 27) +#define SYSCTL_GROUP0_LINK0_UART3 (1 << 28) +#define SYSCTL_GROUP0_LINK0_UART4 (1 << 29) +#define SYSCTL_GROUP0_LINK0_UART5 (1 << 30) +#define SYSCTL_GROUP0_LINK0_UART6 (1 << 11) +#define SYSCTL_GROUP0_LINK1_UART7 (1 << 0) +#define SYSCTL_GROUP0_LINK1_I2C0 (1 << 1) +#define SYSCTL_GROUP0_LINK1_I2C1 (1 << 2) +#define SYSCTL_GROUP0_LINK1_I2C2 (1 << 3) +#define SYSCTL_GROUP0_LINK1_I2C3 (1 << 4) +#define SYSCTL_GROUP0_LINK1_SPI0 (1 << 5) +#define SYSCTL_GROUP0_LINK1_SPI1 (1 << 6) +#define SYSCTL_GROUP0_LINK1_SPI2 (1 << 7) +#define SYSCTL_GROUP0_LINK1_SPI3 (1 << 8) +#define SYSCTL_GROUP0_LINK1_CAN0 (1 << 9) +#define SYSCTL_GROUP0_LINK1_CAN1 (1 << 10) +#define SYSCTL_GROUP0_LINK1_PTPC (1 << 11) +#define SYSCTL_GROUP0_LINK1_ADC0 (1 << 12) +#define SYSCTL_GROUP0_LINK1_ADC1 (1 << 13) +#define SYSCTL_GROUP0_LINK1_ADC2 (1 << 14) +#define SYSCTL_GROUP0_LINK1_DAC0 (1 << 15) +#define SYSCTL_GROUP0_LINK1_ACMP (1 << 16) +#define SYSCTL_GROUP0_LINK1_I2S0 (1 << 17) +#define SYSCTL_GROUP0_LINK1_I2S1 (1 << 18) +#define SYSCTL_GROUP0_LINK1_I2SPDM0 (1 << 19) +#define SYSCTL_GROUP0_LINK1_I2SDAO (1 << 20) +#define SYSCTL_GROUP0_LINK1_MSYN (1 << 21) +#define SYSCTL_GROUP0_LINK1_MOT0 (1 << 22) +#define SYSCTL_GROUP0_LINK1_MOT1 (1 << 23) +#define SYSCTL_GROUP0_LINK1_ETH0 (1 << 24) +#define SYSCTL_GROUP0_LINK1_NTMR0 (1 << 25) +#define SYSCTL_GROUP0_LINK1_SDXC0 (1 << 26) +#define SYSCTL_GROUP0_LINK1_USB0 (1 << 27) +#define SYSCTL_GROUP0_LINK1_REF0 (1 << 28) +#define SYSCTL_GROUP0_LINK1_REF1 (1 << 29) + +#define SYSCTL_RESOURCE_CPU0 (0) +#define SYSCTL_RESOURCE_CPX1 (1) +#define SYSCTL_RESOURCE_EXE0 (2) +#define SYSCTL_RESOURCE_WAK0 (3) +#define SYSCTL_RESOURCE_CPU0_PER (4) +#define SYSCTL_RESOURCE_LOGIC0 (16) +#define SYSCTL_RESOURCE_LOGIC1 (17) +#define SYSCTL_RESOURCE_LOGIC2 (18) +#define SYSCTL_RESOURCE_LOGIC3 (19) +#define SYSCTL_RESOURCE_PMIC (20) +#define SYSCTL_RESOURCE_POW_CPU0 (21) +#define SYSCTL_RESOURCE_RST_SOC (22) +#define SYSCTL_RESOURCE_RST_CPU0 (23) +#define SYSCTL_RESOURCE_XTAL (32) +#define SYSCTL_RESOURCE_PLL0 (33) +#define SYSCTL_RESOURCE_CLK0_PLL0 (34) +#define SYSCTL_RESOURCE_CLK1_PLL0 (35) +#define SYSCTL_RESOURCE_CLK2_PLL0 (36) +#define SYSCTL_RESOURCE_PLL1 (37) +#define SYSCTL_RESOURCE_CLK0_PLL1 (38) +#define SYSCTL_RESOURCE_CLK1_PLL1 (39) +#define SYSCTL_RESOURCE_PLL2 (40) +#define SYSCTL_RESOURCE_CLK0_PLL2 (41) +#define SYSCTL_RESOURCE_CLK1_PLL2 (42) +#define SYSCTL_RESOURCE_PLL0_REF (43) +#define SYSCTL_RESOURCE_PLL1_REF (44) +#define SYSCTL_RESOURCE_PLL2_REF (45) +#define SYSCTL_RESOURCE_MBIST_SOC (48) +#define SYSCTL_RESOURCE_MBIST_CPU (49) +#define SSYCTL_RESOURCE_MBIST_CON (50) +#define SYSCTL_RESOURCE_DFT_START_BUS (51) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64) +#define SYSCTL_RESOURCE_CLK_TOP_MCHTMR0 (65) +#define SYSCTL_RESOURCE_CLK_TOP_FEMC (66) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67) +#define SYSCTL_RESOURCE_CLK_TOP_XPI1 (68)__ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (93) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (94) +#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (95) +#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (96) +#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (97) +#define SYSCTL_RESOURCE_CLK_TOP_ETH0 (98) +#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (99) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (100) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (101) +#define SYSCTL_RESOURCE_CLK_TOP_NTMR0 (102) +#define SYSCTL_RESOURCE_CLK_TOP_SDXC0 (103) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129) +#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130) +#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131) +#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (132) +#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (133) + +#define SYSCTL_RESOURCE_ETH0_MEM (192) +#define SYSCTL_RESOURCE_SDXC0_MEM (193) +#define SYSCTL_RESOURCE_USB0_MEM (194) +#define SYSCTL_RESOURCE_RAM0_MEM (195) +#define SYSCTL_RESOURCE_AHBP_MEM (196) +#define SYSCTL_RESOURCE_FEMC_MEM (197) +#define SYSCTL_RESOURCE_ROM0_MEM (198) +#define SYSCTL_RESOURCE_XPI0_MEM (199) +#define SYSCTL_RESOURCE_XPI1_MEM (200) +#define SYSCTL_RESOURCE_CAN0_MEM (201) +#define SYSCTL_RESOURCE_CAN1_MEM (202) +#define SYSCTL_RESOURCE_I2S0_MEM (203) +#define SYSCTL_RESOURCE_I2S1_MEM (204) +#define SYSCTL_RESOURCE_PDM0_MEM (205) +#define SYSCTL_RESOURCE_SDP0_MEM (206) +#define SYSCTL_RESOURCE_FFA0_MEM (207) +#define SYSCTL_RESOURCE_CPX_MEM (208) +#define SYSCTL_RESOURCE_CORE_MEM (209) +#define SYSCTL_RESOURCE_LMM0_MEM (210) + +#define SYSCTL_RESOURCE_LINKABLE_START (256) +#define SYSCTL_RESOURCE_AHBP (256) +#define SYSCTL_RESOURCE_AXIS (257) +#define SYSCTL_RESOURCE_AXIC (258) +#define SYSCTL_RESOURCE_FEMC (259) +#define SYSCTL_RESOURCE_ROM0 (260) +#define SYSCTL_RESOURCE_LMM0 (261) +#define SYSCTL_RESOURCE_RAM0 (262) +#define SYSCTL_RESOURCE_MCHTMR0 (263) +#define SYSCTL_RESOURCE_XPI0 (264) +#define SYSCTL_RESOURCE_XPI1 (265) +#define SYSCTL_RESOURCE_SDP0 (266) +#define SYSCTL_RESOURCE_RNG0 (267) +#define SYSCTL_RESOURCE_KMAN (268) +#define SYSCTL_RESOURCE_DMA0 (269) +#define SYSCTL_RESOURCE_DMA1 (270) +#define SYSCTL_RESOURCE_FFA0 (271) +#define SYSCTL_RESOURCE_GPIO (272) +#define SYSCTL_RESOURCE_MBX0 (273) +#define SYSCTL_RESOURCE_WDG0 (274) +#define SYSCTL_RESOURCE_WDG1 (275) +#define SYSCTL_RESOURCE_TSNS (276) +#define SYSCTL_RESOURCE_GPTMR0 (277) +#define SYSCTL_RESOURCE_GPTMR1 (278) +#define SYSCTL_RESOURCE_GPRMR2 (279) +#define SYSCTL_RESOURCE_GPTMR3 (280) +#define SYSCTL_RESOURCE_UART0 (281) +#define SYSCTL_RESOURCE_UART1 (282) +#define SYSCTL_RESOURCE_UART2 (283) +#define SYSCTL_RESOURCE_UART3 (284) +#define SYSCTL_RESOURCE_UART4 (285) +#define SYSCTL_RESOURCE_UART5 (286) +#define SYSCTL_RESOURCE_UART6 (287) +#define SYSCTL_RESOURCE_UART7 (288) +#define SYSCTL_RESOURCE_I2C0 (289) +#define SYSCTL_RESOURCE_I2C1 (290) +#define SYSCTL_RESOURCE_I2C2 (291) +#define SYSCTL_RESOURCE_I2C3 (292) +#define SYSCTL_RESOURCE_SPI0 (293) +#define SYSCTL_RESOURCE_SPI1 (294) +#define SYSCTL_RESOURCE_SPI2 (295) +#define SYSCTL_RESOURCE_SPI3 (296) +#define SYSCTL_RESOURCE_CAN0 (297) +#define SYSCTL_RESOURCE_CAN1 (298) +#define SYSCTL_RESOURCE_PTPC (299) +#define SYSCTL_RESOURCE_ADC0 (300) +#define SYSCTL_RESOURCE_ADC1 (301) +#define SYSCTL_RESOURCE_ADC2 (302) +#define SYSCTL_RESOURCE_DAC0 (303) +#define SYSCTL_RESOURCE_ACMP (304) +#define SYSCTL_RESOURCE_I2S0 (305) +#define SYSCTL_RESOURCE_I2S1 (306) +#define SYSCTL_RESOURCE_I2SPDM0 (307) +#define SYSCTL_RESOURCE_I2SDAO (308) +#define SYSCTL_RESOURCE_MSYN (309) +#define SYSCTL_RESOURCE_MOT0 (310) +#define SYSCTL_RESOURCE_MOT1 (311) +#define SYSCTL_RESOURCE_ETH0 (312) +#define SYSCTL_RESOURCE_NTMR0 (313) +#define SYSCTL_RESOURCE_SDXC0 (314) +#define SYSCTL_RESOURCE_USB0 (315) +#define SYSCTL_RESOURCE_REF0 (316) +#define SYSCTL_RESOURCE_REF1 (317) +#define SYSCTL_RESOURCE_LINKABLE_END (317) + +#define CLOCK_NODE_MCHTMR0 (0) +#define CLOCK_NODE_FEMC (1) +#define CLOCK_NODE_XPI0 (2) +#define CLOCK_NODE_XPI1 (3) +#define CLOCK_NODE_GPTMR0 (4) +#define CLOCK_NODE_GPTMR1 (5) +#define CLOCK_NODE_GPTMR2 (6) +#define CLOCK_NODE_GPTMR3 (7) +#define CLOCK_NODE_UART0 (8) +#define CLOCK_NODE_UART1 (9) +#define CLOCK_NODE_UART2 (10) +#define CLOCK_NODE_UART3 (11) +#define CLOCK_NODE_UART4 (12) +#define CLOCK_NODE_UART5 (13) +#define CLOCK_NODE_UART6 (14) +#define CLOCK_NODE_UART7 (15) +#define CLOCK_NODE_I2C0 (16) +#define CLOCK_NODE_I2C1 (17) +#define CLOCK_NODE_I2C2 (18) +#define CLOCK_NODE_I2C3 (19) +#define CLOCK_NODE_SPI0 (20) +#define CLOCK_NODE_SPI1 (21) +#define CLOCK_NODE_SPI2 (22) +#define CLOCK_NODE_SPI3 (23) +#define CLOCK_NODE_CAN0 (24) +#define CLOCK_NODE_CAN1 (25) +#define CLOCK_NODE_PTPC (26) +#define CLOCK_NODE_ANA0 (27) +#define CLOCK_NODE_ANA1 (28) +#define CLOCK_NODE_ANA2 (29) +#define CLOCK_NODE_ANA3 (30) +#define CLOCK_NODE_AUD0 (31) +#define CLOCK_NODE_AUD1 (32) +#define CLOCK_NODE_ETH0 (33) +#define CLOCK_NODE_PTP0 (34) +#define CLOCK_NODE_REF0 (35) +#define CLOCK_NODE_REF1 (36) +#define CLOCK_NODE_NTMR0 (37) +#define CLOCK_NODE_SDXC0 (38) + +#define CLOCK_NODE_ADC0 (0) +#define CLOCK_NODE_ADC1 (1) +#define CLOCK_NODE_ADC2 (2) + +#define CLOCK_NODE_DAC0 (1) + +#define CLOCK_NODE_I2S0 (0) +#define CLOCK_NODE_I2S1 (1) + +#define CLOCK_NODE_CORE_START (252) +#define CLOCK_NODE_CPU0 (252) +#define CLOCK_NODE_AXI (253) +#define CLOCK_NODE_AHB (254) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H */ Review Comment: ```suggestion #endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H */ ``` ########## boards/risc-v/hpm6000/hpm6360evk/scripts/flash.script: ########## @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/risc-v/hpm6750/hpm6750evk2/scripts/ld.script Review Comment: ```suggestion * boards/risc-v/hpm6000/hpm6360evk/scripts/ld.script ``` General comment: Maybe use `6xxx` instead of `6000`? Or something similar ########## arch/risc-v/src/hpm6000/hpm_ioc.h: ########## @@ -0,0 +1,185 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_ioc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + + #ifndef __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H + #define __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> + +#include "hardware/hpm_memorymap.h" +#include "hardware/hpm_ioc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 16-bit Encoding: + * + * AAAA ARRR ODDD LSST + */ + +/* Peripheral Alternate Function: + * AAAA A... .... .... + */ + +#define PAD_ALT_SHIFT (11) /* Bits 11-15: Peripheral alternate function */ +#define PAD_ALT_MASK (0x1f << PAD_ALT_SHIFT) +# define PAD_ALT0 (0 << PAD_ALT_SHIFT) +# define PAD_ALT1 (1 << PAD_ALT_SHIFT) +# define PAD_ALT2 (2 << PAD_ALT_SHIFT) +# define PAD_ALT3 (3 << PAD_ALT_SHIFT) +# define PAD_ALT4 (4 << PAD_ALT_SHIFT) +# define PAD_ALT5 (5 << PAD_ALT_SHIFT) +# define PAD_ALT6 (6 << PAD_ALT_SHIFT) +# define PAD_ALT7 (7 << PAD_ALT_SHIFT) +# define PAD_ALT8 (8 << PAD_ALT_SHIFT) +# define PAD_ALT9 (9 << PAD_ALT_SHIFT) +# define PAD_ALT10 (10 << PAD_ALT_SHIFT) +# define PAD_ALT11 (11 << PAD_ALT_SHIFT) +# define PAD_ALT12 (12 << PAD_ALT_SHIFT) +# define PAD_ALT13 (13 << PAD_ALT_SHIFT) +# define PAD_ALT14 (14 << PAD_ALT_SHIFT) +# define PAD_ALT15 (15 << PAD_ALT_SHIFT) +# define PAD_ALT16 (16 << PAD_ALT_SHIFT) +# define PAD_ALT17 (17 << PAD_ALT_SHIFT) +# define PAD_ALT18 (18 << PAD_ALT_SHIFT) +# define PAD_ALT19 (19 << PAD_ALT_SHIFT) +# define PAD_ALT20 (20 << PAD_ALT_SHIFT) +# define PAD_ALT21 (21 << PAD_ALT_SHIFT) +# define PAD_ALT22 (22 << PAD_ALT_SHIFT) +# define PAD_ALT23 (23 << PAD_ALT_SHIFT) +# define PAD_ALT24 (24 << PAD_ALT_SHIFT) +# define PAD_ALT25 (25 << PAD_ALT_SHIFT) +# define PAD_ALT26 (26 << PAD_ALT_SHIFT) +# define PAD_ALT27 (27 << PAD_ALT_SHIFT) +# define PAD_ALT28 (28 << PAD_ALT_SHIFT) +# define PAD_ALT29 (29 << PAD_ALT_SHIFT) +# define PAD_ALT30 (30 << PAD_ALT_SHIFT) +# define PAD_ALT31 (31 << PAD_ALT_SHIFT) + +/* Output Pull Up/Down: + * + * .... RRRR .... .... + */ + +#define _PAD_PULLTYPE_SHIFT (8) /* Bits 8: Pull up/down type */ +#define _PAD_PULLTYPE_MASK (1 << _PAD_PULLTYPE_SHIFT) +# define _PAD_PULL_KEEP (0 << _PAD_PULLTYPE_SHIFT) /* Output determined by keeper */ +# define _PAD_PULL_ENABLE (1 << _PAD_PULLTYPE_SHIFT) /* Output pulled up or down */ + +#define _PAD_PULLDESC_SHIFT (9) /* Bits 9-10: Pull up/down description */ +#define _PAD_PULLDESC_MASK (3 << _PAD_PULLDESC_SHIFT) +# define _PAD_PULL_UP_22K (PULL_UP_22K << _PAD_PULLDESC_SHIFT) /* Pull up with 22 KOhm resister */ +# define _PAD_PULL_UP_47K (PULL_UP_47K << _PAD_PULLDESC_SHIFT) /* Pull up with 47 KOhm resister */ +# define _PAD_PULL_UP_100K (PULL_UP_100K << _PAD_PULLDESC_SHIFT) /* Pull up with 100 KOhm resister */ +# define _PAD_PULL_DOWN_100K (PULL_DOWN_100K << _PAD_PULLDESC_SHIFT) /* Pull down with 100 KOhm resister */ + +#define PAD_PULL_SHIFT (8) /* Bits 8-10: Pull up/down selection */ +#define PAD_PULL_MASK (15 << PAD_PULL_SHIFT) +# define PAD_PULL_KEEP _PAD_PULL_KEEP +# define PAD_PULL_UP_22K (_PAD_PULL_ENABLE | _PAD_PULL_UP_22K) +# define PAD_PULL_UP_47K (_PAD_PULL_ENABLE | _PAD_PULL_UP_47K) +# define PAD_PULL_UP_100K (_PAD_PULL_ENABLE | _PAD_PULL_UP_100K) +# define PAD_PULL_DOWN_100K (_PAD_PULL_ENABLE | _PAD_PULL_DOWN_100K) + +/* Open Drain Output: + * + * .... .... O... .... + */ + +#define PAD_CMOS_OUTPUT (0) /* Bit 7: 0=CMOS output */ +#define PAD_OPENDRAIN (1 << 7) /* Bit 7: 1=Enable open-drain output */ + +/* Output Drive Strength: + * + * .... .... .DDD .... + */ + +#define PAD_DRIVE_SHIFT (4) /* Bits 4-6: Output Drive Strength */ +#define PAD_DRIVE_MASK (7 << PAD_DRIVE_SHIFT) +# define PAD_DRIVE_260OHM (DRIVE_260OHM << PAD_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +# define PAD_DRIVE_130OHM (DRIVE_130OHM << PAD_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +# define PAD_DRIVE_88OHM (DRIVE_88OHM << PAD_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +# define PAD_DRIVE_65OHM (DRIVE_65OHM << PAD_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +# define PAD_DRIVE_52OHM (DRIVE_52OHM << PAD_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +# define PAD_DRIVE_43OHM (DRIVE_43OHM << PAD_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +# define PAD_DRIVE_37OHM (DRIVE_37OHM << PAD_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ + +/* Analog pin + * + * .... .... .DDD .... + */ +#define FUNC_ANALOG_SHIFT (4) +#define FUNC_ANALOG_MASK (7 << FUNC_ANALOG_SHIFT) +#define FUNC_ANALOG (0 << FUNC_ANALOG_SHIFT) + +/* Output Slew Rate: + * + * .... .... .... L... + */ + +#define PAD_SLEW_SLOW (0) /* Bit 3: 0=Slow Slew Rate */ +#define PAD_SLEW_FAST (1 << 3) /* Bit 3: 1=Fast Slew Rate */ + +/* Output Speed: + * + * .... .... .... .SS. + */ + +#define PAD_SPEED_SHIFT (1) /* Bits 1-2: Speed */ +#define PAD_SPEED_MASK (3 << PAD_SPEED_SHIFT) +# define PAD_SPEED_SLOW (SPEED_SLOW << PAD_SPEED_SHIFT) /* Low frequency (50 MHz) */ +# define PAD_SPEED_MEDIUM (SPEED_MEDIUM << PAD_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ +# define PAD_SPEED_FAST (SPEED_FAST << PAD_SPEED_SHIFT) /* Fast frequency */ +# define PAD_SPEED_MAX (SPEED_MAX << PAD_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ + +/* Input Schmitt Trigger: + * + * .... .... .... ...T + */ + +#define PAD_CMOS_INPUT (0) /* Bit 0: 0=CMOS input */ +#define PAD_SCHMITT_TRIGGER (1 << 0) /* Bit 0: 1=Enable Schmitt trigger if input */ + +#define IOC_FUNC_CTL_(port, pin) (HPM_IOC_BASE + port * 0x0100 + pin * 0x0008 + 0x0000) +#define IOC_PAD_CTL_(port, pin) (HPM_IOC_BASE + port * 0x0100 + pin * 0x0008 + 0x0004) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The smallest integer type that can hold the IOMUX encoding */ + +typedef uint16_t ioc_pinset_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +unsigned int hpm_iocpad_map(unsigned int iocpad); +int hpm_iocpad_configure(uintptr_t padctl, ioc_pinset_t ioset); + +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H */ Review Comment: ```suggestion #endif /* __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H */ ``` -- This is an automated message from the Apache Git Service. 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