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xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new af247276d5 Fix nuttx coding style
af247276d5 is described below
commit af247276d5285c8a279abcd50ceb11f4152476c5
Author: simbit18 <101105604+simbi...@users.noreply.github.com>
AuthorDate: Mon Jul 10 18:08:32 2023 +0200
Fix nuttx coding style
Remove TABs
Fix indentation
---
arch/arm/src/cxd56xx/cxd56_i2c.c | 2 +-
arch/arm/src/cxd56xx/cxd56_powermgr.h | 200 ++++++++++-----------
arch/arm/src/cxd56xx/hardware/cxd56_adc.h | 70 ++++----
arch/arm/src/lpc2378/lpc23xx_uart.h | 4 +-
arch/arm/src/phy62xx/rom_sym_def.h | 20 +--
arch/arm/src/rp2040/rp2040_i2c.c | 2 +-
arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h | 44 ++---
arch/arm/src/sama5/hardware/sam_sdmmc.h | 8 +-
arch/arm/src/samd5e5/hardware/sam_tc.h | 182 +++++++++----------
arch/arm/src/samd5e5/sam_port.h | 4 +-
arch/arm/src/stm32/hardware/stm32_rng.h | 6 +-
.../src/stm32/hardware/stm32f33xxx_pinmap_legacy.h | 2 +-
arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h | 2 +-
.../src/stm32/hardware/stm32f37xxx_pinmap_legacy.h | 2 +-
arch/arm/src/stm32h7/hardware/stm32_fdcan.h | 4 +-
arch/arm/src/stm32h7/hardware/stm32_lptim.h | 2 +-
arch/arm/src/stm32h7/hardware/stm32h7b3xx_flash.h | 28 +--
arch/arm/src/stm32h7/stm32_spi_slave.c | 4 +-
arch/arm/src/stm32h7/stm32_tim_lowerhalf.c | 2 +-
19 files changed, 294 insertions(+), 294 deletions(-)
diff --git a/arch/arm/src/cxd56xx/cxd56_i2c.c b/arch/arm/src/cxd56xx/cxd56_i2c.c
index ebdddf3a74..bcb517696f 100644
--- a/arch/arm/src/cxd56xx/cxd56_i2c.c
+++ b/arch/arm/src/cxd56xx/cxd56_i2c.c
@@ -60,7 +60,7 @@
#define I2C_TIMEOUT (20*1000/CONFIG_USEC_PER_TICK) /* 20 mS */
#define I2C_DEFAULT_FREQUENCY 400000
-#define I2C_FIFO_MAX_SIZE 32
+#define I2C_FIFO_MAX_SIZE 32
#define I2C_INTR_ENABLE ((INTR_STOP_DET) | \
(INTR_TX_ABRT) | \
diff --git a/arch/arm/src/cxd56xx/cxd56_powermgr.h
b/arch/arm/src/cxd56xx/cxd56_powermgr.h
index 07fee64084..52ba26dd66 100644
--- a/arch/arm/src/cxd56xx/cxd56_powermgr.h
+++ b/arch/arm/src/cxd56xx/cxd56_powermgr.h
@@ -66,7 +66,7 @@
#define PM_DOMAIN_SYSIOP (0x20000000ul)
#define PM_DOMAIN_HOSTIF (0x40000000ul)
#define PM_DOMAIN_PMU (0x60000000ul)
-#define PM_DOMAIN_SCU (0x80000000ul)
+#define PM_DOMAIN_SCU (0x80000000ul)
#define PM_DOMAIN_APP (0xA0000000ul)
#define PM_DOMAIN_GPS (0xC0000000ul)
#define PM_DOMAIN_MASK (0xE0000000ul)
@@ -157,142 +157,142 @@
/* SYSIOP */
-#define PM_CLOCK_SYS_CTRL_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B)
-#define PM_CLOCK_SYSPLL_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B)
-#define PM_CLOCK_SYS_CPU_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B)
-#define PM_CLOCK_SYS_CPU_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B)
-#define PM_CLOCK_SYS_AHB_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B |
PM_CLOCK_SYS_AHB_DIV_B)
-#define PM_CLOCK_SYS_APB_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B |
PM_CLOCK_SYS_AHB_DIV_B | PM_CLOCK_SYS_APB_DIV_B)
-#define PM_CLOCK_SYS_COMIF_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_COMIF_DIV_B)
-#define PM_CLOCK_SYS_UART1_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_COMIF_DIV_B |
PM_CLOCK_SYS_UART1_SEL_B)
-#define PM_CLOCK_SYS_SFC_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_SFC_DIV_B)
-#define PM_CLOCK_PMU_RTC_PCLK_SEL (PM_DOMAIN_SYSIOP |
PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B |
PM_CLOCK_SYS_CPU_DIV_B| PM_CLOCK_SYS_AHB_DIV_B | PM_CLOCK_SYS_APB_DIV_B |
PM_CLOCK_PMU_RTC_PCLK_SEL_B)
+#define PM_CLOCK_SYS_CTRL_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B)
+#define PM_CLOCK_SYSPLL_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B)
+#define PM_CLOCK_SYS_CPU_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B)
+#define PM_CLOCK_SYS_CPU_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B)
+#define PM_CLOCK_SYS_AHB_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B |
PM_CLOCK_SYS_AHB_DIV_B)
+#define PM_CLOCK_SYS_APB_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B |
PM_CLOCK_SYS_AHB_DIV_B | PM_CLOCK_SYS_APB_DIV_B)
+#define PM_CLOCK_SYS_COMIF_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_COMIF_DIV_B)
+#define PM_CLOCK_SYS_UART1_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_COMIF_DIV_B |
PM_CLOCK_SYS_UART1_SEL_B)
+#define PM_CLOCK_SYS_SFC_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_SFC_DIV_B)
+#define PM_CLOCK_PMU_RTC_PCLK_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B
| PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B|
PM_CLOCK_SYS_AHB_DIV_B | PM_CLOCK_SYS_APB_DIV_B | PM_CLOCK_PMU_RTC_PCLK_SEL_B)
/* HOSTIF */
-#define PM_CLOCK_HIF_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B)
-#define PM_CLOCK_HIF_DIV (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B)
-#define PM_CLOCK_HIF_SEL2 (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B |
PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B)
-#define PM_CLOCK_HIF_UART0_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B |
PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B | PM_CLOCK_HIF_UART0_SEL_B)
-#define PM_CLOCK_HIF_I2C_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B |
PM_CLOCK_HIF_DIV_B | PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B |
PM_CLOCK_HIF_I2C_SEL_B)
+#define PM_CLOCK_HIF_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B)
+#define PM_CLOCK_HIF_DIV (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B)
+#define PM_CLOCK_HIF_SEL2 (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B |
PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B)
+#define PM_CLOCK_HIF_UART0_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B |
PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B | PM_CLOCK_HIF_UART0_SEL_B)
+#define PM_CLOCK_HIF_I2C_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B |
PM_CLOCK_HIF_DIV_B | PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B |
PM_CLOCK_HIF_I2C_SEL_B)
/* SCU */
-#define PM_CLOCK_SCU_XOSC_DIV (PM_DOMAIN_SCU | PM_CLOCK_SCU_XOSC_DIV_B)
-#define PM_CLOCK_SCU_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_XOSC_DIV_B |
PM_CLOCK_SCU_32K_SEL_B | PM_CLOCK_SCU_SEL_B)
-#define PM_CLOCK_SCU_32K_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B)
-#define PM_CLOCK_SCU_HPADC_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B |
PM_CLOCK_SCU_HPADC_SEL_B)
-#define PM_CLOCK_SCU_LPADC_DIV (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B |
PM_CLOCK_SCU_LPADC_DIV_B)
+#define PM_CLOCK_SCU_XOSC_DIV (PM_DOMAIN_SCU | PM_CLOCK_SCU_XOSC_DIV_B)
+#define PM_CLOCK_SCU_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_XOSC_DIV_B |
PM_CLOCK_SCU_32K_SEL_B | PM_CLOCK_SCU_SEL_B)
+#define PM_CLOCK_SCU_32K_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B)
+#define PM_CLOCK_SCU_HPADC_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B |
PM_CLOCK_SCU_HPADC_SEL_B)
+#define PM_CLOCK_SCU_LPADC_DIV (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B |
PM_CLOCK_SCU_LPADC_DIV_B)
/* APP */
-#define PM_CLOCK_APP_SYSPLL_DIV (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_APP_SYSPLL_DIV_B)
-#define PM_CLOCK_APP_SEL (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B)
-#define PM_CLOCK_APP_AUD_MCLK_DIV (PM_DOMAIN_APP |
PM_CLOCK_APP_AUD_MCLK_DIV_B)
-#define PM_CLOCK_APP_AUD_MCLK_SEL (PM_DOMAIN_APP |
PM_CLOCK_APP_AUD_MCLK_DIV_B | PM_CLOCK_APP_AUD_MCLK_SEL_B)
-#define PM_CLOCK_APP_AHB_GEAR (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B |
PM_CLOCK_APP_AHB_GEAR_B)
-#define PM_CLOCK_APP_UART_GEAR (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B |
PM_CLOCK_APP_UART_GEAR_B)
-#define PM_CLOCK_APP_SPI_GEAR (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B |
PM_CLOCK_APP_SPI_GEAR_B)
-#define PM_CLOCK_APP_WSPI_GEAR (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B |
PM_CLOCK_APP_WSPI_GEAR_B)
-#define PM_CLOCK_APP_SDIO_GEAR (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B |
PM_CLOCK_APP_SDIO_GEAR_B)
-#define PM_CLOCK_APP_USB_GEAR (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B |
PM_CLOCK_APP_USB_GEAR_B)
-#define PM_CLOCK_APP_VSYNC_GEAR (PM_DOMAIN_APP |
PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B |
PM_CLOCK_APP_VSYNC_GEAR_B)
-#define PM_CLOCK_APP_VSYNC_N_GEAR (PM_DOMAIN_APP |
PM_CLOCK_APP_VSYNC_GEAR_N)
+#define PM_CLOCK_APP_SYSPLL_DIV (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_APP_SYSPLL_DIV_B)
+#define PM_CLOCK_APP_SEL (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B)
+#define PM_CLOCK_APP_AUD_MCLK_DIV (PM_DOMAIN_APP |
PM_CLOCK_APP_AUD_MCLK_DIV_B)
+#define PM_CLOCK_APP_AUD_MCLK_SEL (PM_DOMAIN_APP |
PM_CLOCK_APP_AUD_MCLK_DIV_B | PM_CLOCK_APP_AUD_MCLK_SEL_B)
+#define PM_CLOCK_APP_AHB_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B
|PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_AHB_GEAR_B)
+#define PM_CLOCK_APP_UART_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B
|PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_UART_GEAR_B)
+#define PM_CLOCK_APP_SPI_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B
|PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_SPI_GEAR_B)
+#define PM_CLOCK_APP_WSPI_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B
|PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_WSPI_GEAR_B)
+#define PM_CLOCK_APP_SDIO_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B
|PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_SDIO_GEAR_B)
+#define PM_CLOCK_APP_USB_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B
|PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_USB_GEAR_B)
+#define PM_CLOCK_APP_VSYNC_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B
|PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_VSYNC_GEAR_B)
+#define PM_CLOCK_APP_VSYNC_N_GEAR (PM_DOMAIN_APP | PM_CLOCK_APP_VSYNC_GEAR_N)
/* GPS */
-#define PM_CLOCK_GPS_PLL_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B
| PM_CLOCK_GPS_PLL_SEL_B)
-#define PM_CLOCK_GPS_ACQ_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B
| PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_ACQ_SEL_B)
-#define PM_CLOCK_GPS_ITP_TRK_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B
| PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_ACQ_SEL_B
| PM_CLOCK_GPS_ITP_TRK_SEL_B)
-#define PM_CLOCK_GPS_BB_MODE_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B
| PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B)
-#define PM_CLOCK_GPS_LOGGER_SEL (PM_DOMAIN_GPS |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_LOGGER_SEL_B)
-#define PM_CLOCK_GPS_ITB_FFT_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B
| PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B |
PM_CLOCK_GPS_ITB_FFT_SEL_B)
-#define PM_CLOCK_GPS_BB_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B
| PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_BB_SEL_B)
-#define PM_CLOCK_GPS_PPS_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B
| PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_PPS_SEL_B)
-#define PM_CLOCK_GPS_CPU_DIV (PM_DOMAIN_GPS |
PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B |
PM_CLOCK_GPS_CPU_DIV_B)
-#define PM_CLOCK_GPS_AHB_DIV (PM_DOMAIN_GPS |
PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B |
PM_CLOCK_GPS_CPU_DIV_B | PM_CLOCK_GPS_AHB_DIV_B)
+#define PM_CLOCK_GPS_PLL_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B |
PM_CLOCK_GPS_PLL_SEL_B)
+#define PM_CLOCK_GPS_ACQ_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B |
PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_ACQ_SEL_B)
+#define PM_CLOCK_GPS_ITP_TRK_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B |
PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_ACQ_SEL_B |
PM_CLOCK_GPS_ITP_TRK_SEL_B)
+#define PM_CLOCK_GPS_BB_MODE_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B |
PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B)
+#define PM_CLOCK_GPS_LOGGER_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B |
PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_LOGGER_SEL_B)
+#define PM_CLOCK_GPS_ITB_FFT_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B |
PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B |
PM_CLOCK_GPS_ITB_FFT_SEL_B)
+#define PM_CLOCK_GPS_BB_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B |
PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_BB_SEL_B)
+#define PM_CLOCK_GPS_PPS_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B |
PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_PPS_SEL_B)
+#define PM_CLOCK_GPS_CPU_DIV (PM_DOMAIN_GPS | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_GPS_CPU_DIV_B)
+#define PM_CLOCK_GPS_AHB_DIV (PM_DOMAIN_GPS | PM_CLOCK_SYS_CTRL_SEL_B |
PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_GPS_CPU_DIV_B |
PM_CLOCK_GPS_AHB_DIV_B)
/* PMU */
-#define PM_CLOCK_PMU_SEL (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B)
-#define PM_CLOCK_PMU_PWCTL_SEL (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B |
PM_CLOCK_PMU_PWCTL_SEL_B)
-#define PM_CLOCK_PMU_PWCTL_DIV (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B |
PM_CLOCK_PMU_PWCTL_SEL_B | PM_CLOCK_PMU_PWCTL_DIV_B )
+#define PM_CLOCK_PMU_SEL (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B)
+#define PM_CLOCK_PMU_PWCTL_SEL (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B |
PM_CLOCK_PMU_PWCTL_SEL_B)
+#define PM_CLOCK_PMU_PWCTL_DIV (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B |
PM_CLOCK_PMU_PWCTL_SEL_B | PM_CLOCK_PMU_PWCTL_DIV_B )
/****************************************************************************
* cxd56_pm_getclock & cxd56_pm_register_callback Interface Define
****************************************************************************/
-#define PM_CLOCK_SYS_CTRL PM_CLOCK_SYS_CTRL_SEL
-#define PM_CLOCK_SYSPLL PM_CLOCK_SYSPLL_DIV
-#define PM_CLOCK_SYS_CPU PM_CLOCK_SYS_CPU_DIV
-#define PM_CLOCK_SYS_AHB PM_CLOCK_SYS_AHB_DIV
-#define PM_CLOCK_SYS_APB PM_CLOCK_SYS_APB_DIV
-#define PM_CLOCK_SYS_COMIF PM_CLOCK_SYS_COMIF_DIV
-#define PM_CLOCK_SYS_UART1 PM_CLOCK_SYS_UART1_SEL
-#define PM_CLOCK_SYS_SFC PM_CLOCK_SYS_SFC_DIV
-#define PM_CLOCK_XOSC (PM_DOMAIN_SYSIOP | 0x00100000ul)
-#define PM_CLOCK_RCOSC (PM_DOMAIN_SYSIOP | 0x00200000ul)
-#define PM_CLOCK_RTC (PM_DOMAIN_SYSIOP | 0x00080000ul)
-#define PM_CLOCK_PMU_I2C PM_CLOCK_PMU_RTC_PCLK_SEL
+#define PM_CLOCK_SYS_CTRL PM_CLOCK_SYS_CTRL_SEL
+#define PM_CLOCK_SYSPLL PM_CLOCK_SYSPLL_DIV
+#define PM_CLOCK_SYS_CPU PM_CLOCK_SYS_CPU_DIV
+#define PM_CLOCK_SYS_AHB PM_CLOCK_SYS_AHB_DIV
+#define PM_CLOCK_SYS_APB PM_CLOCK_SYS_APB_DIV
+#define PM_CLOCK_SYS_COMIF PM_CLOCK_SYS_COMIF_DIV
+#define PM_CLOCK_SYS_UART1 PM_CLOCK_SYS_UART1_SEL
+#define PM_CLOCK_SYS_SFC PM_CLOCK_SYS_SFC_DIV
+#define PM_CLOCK_XOSC (PM_DOMAIN_SYSIOP | 0x00100000ul)
+#define PM_CLOCK_RCOSC (PM_DOMAIN_SYSIOP | 0x00200000ul)
+#define PM_CLOCK_RTC (PM_DOMAIN_SYSIOP | 0x00080000ul)
+#define PM_CLOCK_PMU_I2C PM_CLOCK_PMU_RTC_PCLK_SEL
/* HOSTIF */
-#define PM_CLOCK_HIF PM_CLOCK_HIF_SEL2
-#define PM_CLOCK_HIF_UART0 PM_CLOCK_HIF_UART0_SEL
-#define PM_CLOCK_HIF_I2C PM_CLOCK_HIF_I2C_SEL
+#define PM_CLOCK_HIF PM_CLOCK_HIF_SEL2
+#define PM_CLOCK_HIF_UART0 PM_CLOCK_HIF_UART0_SEL
+#define PM_CLOCK_HIF_I2C PM_CLOCK_HIF_I2C_SEL
/* SCU */
-#define PM_CLOCK_SCU_XOSC PM_CLOCK_SCU_XOSC_DIV
-#define PM_CLOCK_SCU PM_CLOCK_SCU_SEL
-#define PM_CLOCK_SCU_32K PM_CLOCK_SCU_32K_SEL
-#define PM_CLOCK_SCU_HPADC PM_CLOCK_SCU_HPADC_SEL
-#define PM_CLOCK_SCU_LPADC PM_CLOCK_SCU_LPADC_DIV
+#define PM_CLOCK_SCU_XOSC PM_CLOCK_SCU_XOSC_DIV
+#define PM_CLOCK_SCU PM_CLOCK_SCU_SEL
+#define PM_CLOCK_SCU_32K PM_CLOCK_SCU_32K_SEL
+#define PM_CLOCK_SCU_HPADC PM_CLOCK_SCU_HPADC_SEL
+#define PM_CLOCK_SCU_LPADC PM_CLOCK_SCU_LPADC_DIV
/* APP */
-#define PM_CLOCK_APP_SYSPLL PM_CLOCK_APP_SYSPLL_DIV
-#define PM_CLOCK_APP PM_CLOCK_APP_SEL
-#define PM_CLOCK_APP_AUD PM_CLOCK_APP_AUD_MCLK_SEL
-#define PM_CLOCK_APP_AHB PM_CLOCK_APP_AHB_GEAR
-#define PM_CLOCK_APP_CPU PM_CLOCK_APP_AHB
-#define PM_CLOCK_APP_UART PM_CLOCK_APP_UART_GEAR
-#define PM_CLOCK_APP_SPI PM_CLOCK_APP_SPI_GEAR
-#define PM_CLOCK_APP_WSPI PM_CLOCK_APP_WSPI_GEAR
-#define PM_CLOCK_APP_SDIO PM_CLOCK_APP_SDIO_GEAR
-#define PM_CLOCK_APP_USB PM_CLOCK_APP_USB_GEAR
-#define PM_CLOCK_APP_VSYNC PM_CLOCK_APP_VSYNC_GEAR
-#define PM_CLOCK_APP_VSYNC_N PM_CLOCK_APP_VSYNC_N_GEAR
-#define PM_CLOCK_APP_VSYNC_M PM_CLOCK_APP_VSYNC_GEAR
+#define PM_CLOCK_APP_SYSPLL PM_CLOCK_APP_SYSPLL_DIV
+#define PM_CLOCK_APP PM_CLOCK_APP_SEL
+#define PM_CLOCK_APP_AUD PM_CLOCK_APP_AUD_MCLK_SEL
+#define PM_CLOCK_APP_AHB PM_CLOCK_APP_AHB_GEAR
+#define PM_CLOCK_APP_CPU PM_CLOCK_APP_AHB
+#define PM_CLOCK_APP_UART PM_CLOCK_APP_UART_GEAR
+#define PM_CLOCK_APP_SPI PM_CLOCK_APP_SPI_GEAR
+#define PM_CLOCK_APP_WSPI PM_CLOCK_APP_WSPI_GEAR
+#define PM_CLOCK_APP_SDIO PM_CLOCK_APP_SDIO_GEAR
+#define PM_CLOCK_APP_USB PM_CLOCK_APP_USB_GEAR
+#define PM_CLOCK_APP_VSYNC PM_CLOCK_APP_VSYNC_GEAR
+#define PM_CLOCK_APP_VSYNC_N PM_CLOCK_APP_VSYNC_N_GEAR
+#define PM_CLOCK_APP_VSYNC_M PM_CLOCK_APP_VSYNC_GEAR
/* GPS */
-#define PM_CLOCK_GPS_PLL PM_CLOCK_GPS_PLL_SEL
-#define PM_CLOCK_GPS_ACQ PM_CLOCK_GPS_ACQ_SEL
-#define PM_CLOCK_GPS_ITP_TRK PM_CLOCK_GPS_ITP_TRK_SEL
-#define PM_CLOCK_GPS_BB_MODE PM_CLOCK_GPS_BB_MODE_SEL
-#define PM_CLOCK_GPS_LOGGER PM_CLOCK_GPS_LOGGER_SEL
-#define PM_CLOCK_GPS_ITB_FFT PM_CLOCK_GPS_ITB_FFT_SEL
-#define PM_CLOCK_GPS_BB PM_CLOCK_GPS_BB_SEL
-#define PM_CLOCK_GPS_PPS PM_CLOCK_GPS_PPS_SEL
-#define PM_CLOCK_GPS_CPU PM_CLOCK_GPS_CPU_DIV
-#define PM_CLOCK_GPS_AHB PM_CLOCK_GPS_AHB_DIV
+#define PM_CLOCK_GPS_PLL PM_CLOCK_GPS_PLL_SEL
+#define PM_CLOCK_GPS_ACQ PM_CLOCK_GPS_ACQ_SEL
+#define PM_CLOCK_GPS_ITP_TRK PM_CLOCK_GPS_ITP_TRK_SEL
+#define PM_CLOCK_GPS_BB_MODE PM_CLOCK_GPS_BB_MODE_SEL
+#define PM_CLOCK_GPS_LOGGER PM_CLOCK_GPS_LOGGER_SEL
+#define PM_CLOCK_GPS_ITB_FFT PM_CLOCK_GPS_ITB_FFT_SEL
+#define PM_CLOCK_GPS_BB PM_CLOCK_GPS_BB_SEL
+#define PM_CLOCK_GPS_PPS PM_CLOCK_GPS_PPS_SEL
+#define PM_CLOCK_GPS_CPU PM_CLOCK_GPS_CPU_DIV
+#define PM_CLOCK_GPS_AHB PM_CLOCK_GPS_AHB_DIV
/* PMU */
-#define PM_CLOCK_PMU PM_CLOCK_PMU_PWCTL_SEL
-#define PM_CLOCK_PMUA PM_CLOCK_PMU_PWCTL_DIV
+#define PM_CLOCK_PMU PM_CLOCK_PMU_PWCTL_SEL
+#define PM_CLOCK_PMUA PM_CLOCK_PMU_PWCTL_DIV
-#define PM_CLOCK_SYS_DMAC PM_CLOCK_SYS_AHB
-#define PM_CLOCK_SYS_SAKE PM_CLOCK_SYS_AHB
-#define PM_CLOCK_SYS_KAKI PM_CLOCK_SYS_AHB
-#define PM_CLOCK_SYS_SPIM PM_CLOCK_SYS_COMIF
-#define PM_CLOCK_SYS_I2CM PM_CLOCK_SYS_COMIF
-#define PM_CLOCK_APP_DMAC PM_CLOCK_APP_AHB_GEAR
-#define PM_CLOCK_APP_SAKE PM_CLOCK_APP_AHB_GEAR
-#define PM_CLOCK_APP_KAKI PM_CLOCK_APP_AHB_GEAR
+#define PM_CLOCK_SYS_DMAC PM_CLOCK_SYS_AHB
+#define PM_CLOCK_SYS_SAKE PM_CLOCK_SYS_AHB
+#define PM_CLOCK_SYS_KAKI PM_CLOCK_SYS_AHB
+#define PM_CLOCK_SYS_SPIM PM_CLOCK_SYS_COMIF
+#define PM_CLOCK_SYS_I2CM PM_CLOCK_SYS_COMIF
+#define PM_CLOCK_APP_DMAC PM_CLOCK_APP_AHB_GEAR
+#define PM_CLOCK_APP_SAKE PM_CLOCK_APP_AHB_GEAR
+#define PM_CLOCK_APP_KAKI PM_CLOCK_APP_AHB_GEAR
-#define PM_CLOCK_CPUID(id) ((0 == (id)) ? PM_CLOCK_SYS_CPU : \
+#define PM_CLOCK_CPUID(id) ((0 == (id)) ? PM_CLOCK_SYS_CPU : \
(1 == (id)) ? PM_CLOCK_GPS_CPU : \
PM_CLOCK_APP_CPU)
diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_adc.h
b/arch/arm/src/cxd56xx/hardware/cxd56_adc.h
index bf3f587f44..7b28a3938d 100644
--- a/arch/arm/src/cxd56xx/hardware/cxd56_adc.h
+++ b/arch/arm/src/cxd56xx/hardware/cxd56_adc.h
@@ -21,40 +21,40 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_ADC_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_ADC_H
-#define SCUADCIF_LPADC_A0 (CXD56_SCU_ADCIF_BASE + 0x200)
-#define SCUADCIF_LPADC_A1 (CXD56_SCU_ADCIF_BASE + 0x204)
-#define SCUADCIF_LPADC_D0 (CXD56_SCU_ADCIF_BASE + 0x210)
-#define SCUADCIF_LPADC_D1 (CXD56_SCU_ADCIF_BASE + 0x214)
-#define SCUADCIF_LPADC_D4 (CXD56_SCU_ADCIF_BASE + 0x21c)
-#define SCUADCIF_LPADC_D5 (CXD56_SCU_ADCIF_BASE + 0x220)
-#define SCUADCIF_LPADC_D6 (CXD56_SCU_ADCIF_BASE + 0x224)
-#define SCUADCIF_LPADC_D2 (CXD56_SCU_ADCIF_BASE + 0x218)
-#define SCUADCIF_HPADC_AC0 (CXD56_SCU_ADCIF_BASE + 0x240)
-#define SCUADCIF_HPADC_AC1 (CXD56_SCU_ADCIF_BASE + 0x244)
-#define SCUADCIF_HPADC_DC (CXD56_SCU_ADCIF_BASE + 0x250)
-#define SCUADCIF_HPADC0_A0 (CXD56_SCU_ADCIF_BASE + 0x280)
-#define SCUADCIF_HPADC0_A1 (CXD56_SCU_ADCIF_BASE + 0x284)
-#define SCUADCIF_HPADC0_A2 (CXD56_SCU_ADCIF_BASE + 0x288)
-#define SCUADCIF_HPADC0_A3 (CXD56_SCU_ADCIF_BASE + 0x28c)
-#define SCUADCIF_HPADC0_D0 (CXD56_SCU_ADCIF_BASE + 0x290)
-#define SCUADCIF_HPADC0_D1 (CXD56_SCU_ADCIF_BASE + 0x294)
-#define SCUADCIF_HPADC0_D2 (CXD56_SCU_ADCIF_BASE + 0x298)
-#define SCUADCIF_HPADC1_A0 (CXD56_SCU_ADCIF_BASE + 0x2c0)
-#define SCUADCIF_HPADC1_A1 (CXD56_SCU_ADCIF_BASE + 0x2c4)
-#define SCUADCIF_HPADC1_A2 (CXD56_SCU_ADCIF_BASE + 0x2c8)
-#define SCUADCIF_HPADC1_A3 (CXD56_SCU_ADCIF_BASE + 0x2cc)
-#define SCUADCIF_HPADC1_D0 (CXD56_SCU_ADCIF_BASE + 0x2d0)
-#define SCUADCIF_HPADC1_D1 (CXD56_SCU_ADCIF_BASE + 0x2d4)
-#define SCUADCIF_HPADC1_D2 (CXD56_SCU_ADCIF_BASE + 0x2d8)
-#define SCUADCIF_LPADC_AT0 (CXD56_SCU_ADCIF_BASE + 0x300)
-#define SCUADCIF_LPADC_AT1 (CXD56_SCU_ADCIF_BASE + 0x304)
-#define SCUADCIF_HPADC_ACT0 (CXD56_SCU_ADCIF_BASE + 0x340)
-#define SCUADCIF_HPADC_ACT1 (CXD56_SCU_ADCIF_BASE + 0x344)
-#define SCUADCIF_HPADC0_AT0 (CXD56_SCU_ADCIF_BASE + 0x380)
-#define SCUADCIF_HPADC0_AT1 (CXD56_SCU_ADCIF_BASE + 0x384)
-#define SCUADCIF_HPADC1_AT0 (CXD56_SCU_ADCIF_BASE + 0x3c0)
-#define SCUADCIF_HPADC1_AT1 (CXD56_SCU_ADCIF_BASE + 0x3c4)
-#define SCUADCIF_ADCIF_DCT (CXD56_SCU_ADCIF_BASE + 0x3d0)
-#define SCUADCIF_SCU_ADCIF_CKPOWER (CXD56_SCU_ADCIF_BASE + 0x3d4)
+#define SCUADCIF_LPADC_A0 (CXD56_SCU_ADCIF_BASE + 0x200)
+#define SCUADCIF_LPADC_A1 (CXD56_SCU_ADCIF_BASE + 0x204)
+#define SCUADCIF_LPADC_D0 (CXD56_SCU_ADCIF_BASE + 0x210)
+#define SCUADCIF_LPADC_D1 (CXD56_SCU_ADCIF_BASE + 0x214)
+#define SCUADCIF_LPADC_D4 (CXD56_SCU_ADCIF_BASE + 0x21c)
+#define SCUADCIF_LPADC_D5 (CXD56_SCU_ADCIF_BASE + 0x220)
+#define SCUADCIF_LPADC_D6 (CXD56_SCU_ADCIF_BASE + 0x224)
+#define SCUADCIF_LPADC_D2 (CXD56_SCU_ADCIF_BASE + 0x218)
+#define SCUADCIF_HPADC_AC0 (CXD56_SCU_ADCIF_BASE + 0x240)
+#define SCUADCIF_HPADC_AC1 (CXD56_SCU_ADCIF_BASE + 0x244)
+#define SCUADCIF_HPADC_DC (CXD56_SCU_ADCIF_BASE + 0x250)
+#define SCUADCIF_HPADC0_A0 (CXD56_SCU_ADCIF_BASE + 0x280)
+#define SCUADCIF_HPADC0_A1 (CXD56_SCU_ADCIF_BASE + 0x284)
+#define SCUADCIF_HPADC0_A2 (CXD56_SCU_ADCIF_BASE + 0x288)
+#define SCUADCIF_HPADC0_A3 (CXD56_SCU_ADCIF_BASE + 0x28c)
+#define SCUADCIF_HPADC0_D0 (CXD56_SCU_ADCIF_BASE + 0x290)
+#define SCUADCIF_HPADC0_D1 (CXD56_SCU_ADCIF_BASE + 0x294)
+#define SCUADCIF_HPADC0_D2 (CXD56_SCU_ADCIF_BASE + 0x298)
+#define SCUADCIF_HPADC1_A0 (CXD56_SCU_ADCIF_BASE + 0x2c0)
+#define SCUADCIF_HPADC1_A1 (CXD56_SCU_ADCIF_BASE + 0x2c4)
+#define SCUADCIF_HPADC1_A2 (CXD56_SCU_ADCIF_BASE + 0x2c8)
+#define SCUADCIF_HPADC1_A3 (CXD56_SCU_ADCIF_BASE + 0x2cc)
+#define SCUADCIF_HPADC1_D0 (CXD56_SCU_ADCIF_BASE + 0x2d0)
+#define SCUADCIF_HPADC1_D1 (CXD56_SCU_ADCIF_BASE + 0x2d4)
+#define SCUADCIF_HPADC1_D2 (CXD56_SCU_ADCIF_BASE + 0x2d8)
+#define SCUADCIF_LPADC_AT0 (CXD56_SCU_ADCIF_BASE + 0x300)
+#define SCUADCIF_LPADC_AT1 (CXD56_SCU_ADCIF_BASE + 0x304)
+#define SCUADCIF_HPADC_ACT0 (CXD56_SCU_ADCIF_BASE + 0x340)
+#define SCUADCIF_HPADC_ACT1 (CXD56_SCU_ADCIF_BASE + 0x344)
+#define SCUADCIF_HPADC0_AT0 (CXD56_SCU_ADCIF_BASE + 0x380)
+#define SCUADCIF_HPADC0_AT1 (CXD56_SCU_ADCIF_BASE + 0x384)
+#define SCUADCIF_HPADC1_AT0 (CXD56_SCU_ADCIF_BASE + 0x3c0)
+#define SCUADCIF_HPADC1_AT1 (CXD56_SCU_ADCIF_BASE + 0x3c4)
+#define SCUADCIF_ADCIF_DCT (CXD56_SCU_ADCIF_BASE + 0x3d0)
+#define SCUADCIF_SCU_ADCIF_CKPOWER (CXD56_SCU_ADCIF_BASE + 0x3d4)
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_ADC_H */
diff --git a/arch/arm/src/lpc2378/lpc23xx_uart.h
b/arch/arm/src/lpc2378/lpc23xx_uart.h
index 97cd3bb809..f6754d82c3 100644
--- a/arch/arm/src/lpc2378/lpc23xx_uart.h
+++ b/arch/arm/src/lpc2378/lpc23xx_uart.h
@@ -78,11 +78,11 @@
/* #define U3_PCLKDIV 1 */
-#define U0_PCLK (CCLK / U0_PCLKDIV)
+#define U0_PCLK (CCLK / U0_PCLKDIV)
/* #define U1_PCLK (CCLK / U1_PCLKDIV) */
-#define U2_PCLK (CCLK / U2_PCLKDIV)
+#define U2_PCLK (CCLK / U2_PCLKDIV)
/* #define U3_PCLK (CCLK / U3_PCLKDIV) */
diff --git a/arch/arm/src/phy62xx/rom_sym_def.h
b/arch/arm/src/phy62xx/rom_sym_def.h
index 2dc844b302..8653250e82 100644
--- a/arch/arm/src/phy62xx/rom_sym_def.h
+++ b/arch/arm/src/phy62xx/rom_sym_def.h
@@ -50,18 +50,18 @@
#define sleep_tick _symrom_sleep_tick
#define g_currentPeerAddrType _symrom_g_currentPeerAddrType
- #define g_rfPhyTxPower _symrom_g_rfPhyTxPower
+ #define g_rfPhyTxPower _symrom_g_rfPhyTxPower
#define ble_main _symrom_ble_main
- #define HCI_LE_Write_Rf_Path_CompensationCmd
_symrom_HCI_LE_Write_Rf_Path_CompensationCmd
- #define HCI_LE_ReadPeerResolvableAddressCmd
_symrom_HCI_LE_ReadPeerResolvableAddressCmd
- #define HCI_LE_AddDevToPeriodicAdvListCmd
_symrom_HCI_LE_AddDevToPeriodicAdvListCmd
- #define HCI_LE_RemovePeriodicAdvListCmd
_symrom_HCI_LE_RemovePeriodicAdvListCmd
- #define HCI_LE_ClearPeriodicAdvListCmd
_symrom_HCI_LE_ClearPeriodicAdvListCmd
- #define HCI_LE_ReadPeriodicAdvListSizeCmd
_symrom_HCI_LE_ReadPeriodicAdvListSizeCmd
- #define HCI_LE_Read_Transmit_PowerCmd
_symrom_HCI_LE_Read_Transmit_PowerCmd
- #define HCI_LE_Read_Rf_Path_CompensationCmd
_symrom_HCI_LE_Read_Rf_Path_CompensationCmd
- #define HCI_LE_Set_Privacy_ModeCmd _symrom_HCI_LE_Set_Privacy_ModeCmd
+ #define HCI_LE_Write_Rf_Path_CompensationCmd
_symrom_HCI_LE_Write_Rf_Path_CompensationCmd
+ #define HCI_LE_ReadPeerResolvableAddressCmd
_symrom_HCI_LE_ReadPeerResolvableAddressCmd
+ #define HCI_LE_AddDevToPeriodicAdvListCmd
_symrom_HCI_LE_AddDevToPeriodicAdvListCmd
+ #define HCI_LE_RemovePeriodicAdvListCmd
_symrom_HCI_LE_RemovePeriodicAdvListCmd
+ #define HCI_LE_ClearPeriodicAdvListCmd _symrom_HCI_LE_ClearPeriodicAdvListCmd
+ #define HCI_LE_ReadPeriodicAdvListSizeCmd
_symrom_HCI_LE_ReadPeriodicAdvListSizeCmd
+ #define HCI_LE_Read_Transmit_PowerCmd _symrom_HCI_LE_Read_Transmit_PowerCmd
+ #define HCI_LE_Read_Rf_Path_CompensationCmd
_symrom_HCI_LE_Read_Rf_Path_CompensationCmd
+ #define HCI_LE_Set_Privacy_ModeCmd _symrom_HCI_LE_Set_Privacy_ModeCmd
#define ll_readPeerIRK _symrom_ll_readPeerIRK
#define ownRandomAddr _symrom_ownRandomAddr
diff --git a/arch/arm/src/rp2040/rp2040_i2c.c b/arch/arm/src/rp2040/rp2040_i2c.c
index 38072da4d8..80d4603465 100644
--- a/arch/arm/src/rp2040/rp2040_i2c.c
+++ b/arch/arm/src/rp2040/rp2040_i2c.c
@@ -56,7 +56,7 @@
#define I2C_TIMEOUT (20*1000/CONFIG_USEC_PER_TICK) /* 20 mS */
#define I2C_DEFAULT_FREQUENCY 400000
-#define I2C_FIFO_MAX_SIZE 16
+#define I2C_FIFO_MAX_SIZE 16
#define I2C_INTR_ENABLE ((RP2040_I2C_IC_INTR_STAT_R_STOP_DET) | \
(RP2040_I2C_IC_INTR_STAT_R_TX_ABRT) | \
diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h
b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h
index 0776c7a591..b77810fe00 100644
--- a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h
+++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h
@@ -36,28 +36,28 @@
/* FTFC Register Offsets ****************************************************/
-#define S32K1XX_FTFC_FSTAT_OFFSET 0x0000
-#define S32K1XX_FTFC_FCNFG_OFFSET 0x0001
-#define S32K1XX_FTFC_FSEC_OFFSET 0x0002
-#define S32K1XX_FTFC_FOPT_OFFSET 0x0003
-#define S32K1XX_FTFC_FCCOB3_OFFSET 0x0004
-#define S32K1XX_FTFC_FCCOB2_OFFSET 0x0005
-#define S32K1XX_FTFC_FCCOB1_OFFSET 0x0006
-#define S32K1XX_FTFC_FCCOB0_OFFSET 0x0007
-#define S32K1XX_FTFC_FCCOB7_OFFSET 0x0008
-#define S32K1XX_FTFC_FCCOB6_OFFSET 0x0009
-#define S32K1XX_FTFC_FCCOB5_OFFSET 0x000a
-#define S32K1XX_FTFC_FCCOB4_OFFSET 0x000b
-#define S32K1XX_FTFC_FCCOBB_OFFSET 0x000c
-#define S32K1XX_FTFC_FCCOBA_OFFSET 0x000d
-#define S32K1XX_FTFC_FCCOB9_OFFSET 0x000e
-#define S32K1XX_FTFC_FCCOB8_OFFSET 0x000f
-#define S32K1XX_FTFC_FPROT3_OFFSET 0x0010
-#define S32K1XX_FTFC_FPROT2_OFFSET 0x0011
-#define S32K1XX_FTFC_FPROT1_OFFSET 0x0012
-#define S32K1XX_FTFC_FPROT0_OFFSET 0x0013
-#define S32K1XX_FTFC_FEPROT_OFFSET 0x0016
-#define S32K1XX_FTFC_FDPROT_OFFSET 0x0017
+#define S32K1XX_FTFC_FSTAT_OFFSET 0x0000
+#define S32K1XX_FTFC_FCNFG_OFFSET 0x0001
+#define S32K1XX_FTFC_FSEC_OFFSET 0x0002
+#define S32K1XX_FTFC_FOPT_OFFSET 0x0003
+#define S32K1XX_FTFC_FCCOB3_OFFSET 0x0004
+#define S32K1XX_FTFC_FCCOB2_OFFSET 0x0005
+#define S32K1XX_FTFC_FCCOB1_OFFSET 0x0006
+#define S32K1XX_FTFC_FCCOB0_OFFSET 0x0007
+#define S32K1XX_FTFC_FCCOB7_OFFSET 0x0008
+#define S32K1XX_FTFC_FCCOB6_OFFSET 0x0009
+#define S32K1XX_FTFC_FCCOB5_OFFSET 0x000a
+#define S32K1XX_FTFC_FCCOB4_OFFSET 0x000b
+#define S32K1XX_FTFC_FCCOBB_OFFSET 0x000c
+#define S32K1XX_FTFC_FCCOBA_OFFSET 0x000d
+#define S32K1XX_FTFC_FCCOB9_OFFSET 0x000e
+#define S32K1XX_FTFC_FCCOB8_OFFSET 0x000f
+#define S32K1XX_FTFC_FPROT3_OFFSET 0x0010
+#define S32K1XX_FTFC_FPROT2_OFFSET 0x0011
+#define S32K1XX_FTFC_FPROT1_OFFSET 0x0012
+#define S32K1XX_FTFC_FPROT0_OFFSET 0x0013
+#define S32K1XX_FTFC_FEPROT_OFFSET 0x0016
+#define S32K1XX_FTFC_FDPROT_OFFSET 0x0017
#define S32K1XX_FTFC_FCSESTAT_OFFSET 0x002c
#define S32K1XX_FTFC_FERSTAT_OFFSET 0x002e
#define S32K1XX_FTFC_FERCNFG_OFFSET 0x002f
diff --git a/arch/arm/src/sama5/hardware/sam_sdmmc.h
b/arch/arm/src/sama5/hardware/sam_sdmmc.h
index 9fe4f12d2c..8f3d3de8df 100644
--- a/arch/arm/src/sama5/hardware/sam_sdmmc.h
+++ b/arch/arm/src/sama5/hardware/sam_sdmmc.h
@@ -513,9 +513,9 @@
#define SDMMC_MAX_DIV_SPEC_3 2046
/* Software Reset Register */
-#define SDMMC_RESET_ALL 0x01
-#define SDMMC_RESET_CMD 0x02
-#define SDMMC_RESET_DATA 0x04
+#define SDMMC_RESET_ALL 0x01
+#define SDMMC_RESET_CMD 0x02
+#define SDMMC_RESET_DATA 0x04
/* Host Control 2 Register */
#define SDMMC_UHSMS_MASK (7) /* Bits 0-2: UHS Mode
Select */
@@ -600,7 +600,7 @@ enum bus_mode
* Buffer Boundary pause event.
*/
-#define SDMMC_DEFAULT_BOUNDARY_SIZE (512 * 1024)
+#define SDMMC_DEFAULT_BOUNDARY_SIZE (512 * 1024)
/****************************************************************************
* Public Types
diff --git a/arch/arm/src/samd5e5/hardware/sam_tc.h
b/arch/arm/src/samd5e5/hardware/sam_tc.h
index 6640fbc606..fe35b901fd 100644
--- a/arch/arm/src/samd5e5/hardware/sam_tc.h
+++ b/arch/arm/src/samd5e5/hardware/sam_tc.h
@@ -82,25 +82,25 @@
#define SAM_TC0_INTENSET (SAM_TC0_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC0_INTFLAG (SAM_TC0_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC0_STATUS (SAM_TC0_BASE+SAM_TC_STATUS_OFFSET)
-#define SAM_TC0_WAVE
(SAM_TC0_BASE+SAM_TC_WAVE_OFFSET)
-#define SAM_TC0_DRVCTRL
(SAM_TC0_BASE+SAM_TC_DRVCTRL_OFFSET)
+#define SAM_TC0_WAVE (SAM_TC0_BASE+SAM_TC_WAVE_OFFSET)
+#define SAM_TC0_DRVCTRL (SAM_TC0_BASE+SAM_TC_DRVCTRL_OFFSET)
#define SAM_TC0_DBGCTRL (SAM_TC0_BASE+SAM_TC_DBGCTRL_OFFSET)
-#define SAM_TC0_SYNCBUSY
(SAM_TC0_BASE+SAM_TC_SYNCBUSY_OFFSET)
+#define SAM_TC0_SYNCBUSY (SAM_TC0_BASE+SAM_TC_SYNCBUSY_OFFSET)
#define SAM_TC0_COUNT (SAM_TC0_BASE+SAM_TC_COUNT_OFFSET)
-#define SAM_TC0_COUNT8_PER
(SAM_TC0_BASE+SAM_TC_COUNT8_PER_OFFSET)
+#define SAM_TC0_COUNT8_PER (SAM_TC0_BASE+SAM_TC_COUNT8_PER_OFFSET)
#define SAM_TC0_COUNT8_CC0 (SAM_TC0_BASE+SAM_TC_COUNT8_CC0_OFFSET)
#define SAM_TC0_COUNT8_CC1 (SAM_TC0_BASE+SAM_TC_COUNT8_CC1_OFFSET)
-#define SAM_TC0_COUNT8_PERBUF
(SAM_TC0_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
-#define SAM_TC0_COUNT8_CCBUF0
(SAM_TC0_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
-#define SAM_TC0_COUNT8_CCBUF1
(SAM_TC0_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
+#define SAM_TC0_COUNT8_PERBUF
(SAM_TC0_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
+#define SAM_TC0_COUNT8_CCBUF0
(SAM_TC0_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
+#define SAM_TC0_COUNT8_CCBUF1
(SAM_TC0_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
#define SAM_TC0_COUNT16_CC0 (SAM_TC0_BASE+SAM_TC_COUNT16_CC0_OFFSET)
#define SAM_TC0_COUNT16_CC1 (SAM_TC0_BASE+SAM_TC_COUNT16_CC1_OFFSET)
-#define SAM_TC0_COUNT16_CCBUF0
(SAM_TC0_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
-#define SAM_TC0_COUNT16_CCBUF1
(SAM_TC0_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
+#define SAM_TC0_COUNT16_CCBUF0
(SAM_TC0_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
+#define SAM_TC0_COUNT16_CCBUF1
(SAM_TC0_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
#define SAM_TC0_COUNT32_CC0 (SAM_TC0_BASE+SAM_TC_COUNT32_CC0_OFFSET)
#define SAM_TC0_COUNT32_CC1 (SAM_TC0_BASE+SAM_TC_COUNT32_CC1_OFFSET)
-#define SAM_TC0_COUNT32_CCBUF0
(SAM_TC0_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
-#define SAM_TC0_COUNT32_CCBUF1
(SAM_TC0_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
+#define SAM_TC0_COUNT32_CCBUF0
(SAM_TC0_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
+#define SAM_TC0_COUNT32_CCBUF1
(SAM_TC0_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
#define SAM_TC1_CTRLA (SAM_TC1_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC1_CTRLBCLR (SAM_TC1_BASE+SAM_TC_CTRLBCLR_OFFSET)
@@ -110,25 +110,25 @@
#define SAM_TC1_INTENSET (SAM_TC1_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC1_INTFLAG (SAM_TC1_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC1_STATUS (SAM_TC1_BASE+SAM_TC_STATUS_OFFSET)
-#define SAM_TC1_WAVE (SAM_TC1_BASE+SAM_TC_WAVE_OFFSET)
-#define SAM_TC1_DRVCTRL
(SAM_TC1_BASE+SAM_TC_DRVCTRL_OFFSET)
+#define SAM_TC1_WAVE (SAM_TC1_BASE+SAM_TC_WAVE_OFFSET)
+#define SAM_TC1_DRVCTRL (SAM_TC1_BASE+SAM_TC_DRVCTRL_OFFSET)
#define SAM_TC1_DBGCTRL (SAM_TC1_BASE+SAM_TC_DBGCTRL_OFFSET)
-#define SAM_TC1_SYNCBUSY (SAM_TC1_BASE+SAM_TC_SYNCBUSY_OFFSET)
+#define SAM_TC1_SYNCBUSY (SAM_TC1_BASE+SAM_TC_SYNCBUSY_OFFSET)
#define SAM_TC1_COUNT (SAM_TC1_BASE+SAM_TC_COUNT_OFFSET)
-#define SAM_TC1_COUNT8_PER
(SAM_TC1_BASE+SAM_TC_COUNT8_PER_OFFSET)
+#define SAM_TC1_COUNT8_PER (SAM_TC1_BASE+SAM_TC_COUNT8_PER_OFFSET)
#define SAM_TC1_COUNT8_CC0 (SAM_TC1_BASE+SAM_TC_COUNT8_CC0_OFFSET)
#define SAM_TC1_COUNT8_CC1 (SAM_TC1_BASE+SAM_TC_COUNT8_CC1_OFFSET)
-#define SAM_TC1_COUNT8_PERBUF
(SAM_TC1_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
-#define SAM_TC1_COUNT8_CCBUF0
(SAM_TC1_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
-#define SAM_TC1_COUNT8_CCBUF1 (SAM_TC1_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
+#define SAM_TC1_COUNT8_PERBUF
(SAM_TC1_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
+#define SAM_TC1_COUNT8_CCBUF0
(SAM_TC1_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
+#define SAM_TC1_COUNT8_CCBUF1
(SAM_TC1_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
#define SAM_TC1_COUNT16_CC0 (SAM_TC1_BASE+SAM_TC_COUNT16_CC0_OFFSET)
#define SAM_TC1_COUNT16_CC1 (SAM_TC1_BASE+SAM_TC_COUNT16_CC1_OFFSET)
-#define SAM_TC1_COUNT16_CCBUF0
(SAM_TC1_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
-#define SAM_TC1_COUNT16_CCBUF1
(SAM_TC1_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
+#define SAM_TC1_COUNT16_CCBUF0
(SAM_TC1_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
+#define SAM_TC1_COUNT16_CCBUF1
(SAM_TC1_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
#define SAM_TC1_COUNT32_CC0 (SAM_TC1_BASE+SAM_TC_COUNT32_CC0_OFFSET)
#define SAM_TC1_COUNT32_CC1 (SAM_TC1_BASE+SAM_TC_COUNT32_CC1_OFFSET)
-#define SAM_TC1_COUNT32_CCBUF0
(SAM_TC1_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
-#define SAM_TC1_COUNT32_CCBUF1
(SAM_TC1_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
+#define SAM_TC1_COUNT32_CCBUF0
(SAM_TC1_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
+#define SAM_TC1_COUNT32_CCBUF1
(SAM_TC1_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
#define SAM_TC2_CTRLA (SAM_TC2_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC2_CTRLBCLR (SAM_TC2_BASE+SAM_TC_CTRLBCLR_OFFSET)
@@ -138,25 +138,25 @@
#define SAM_TC2_INTENSET (SAM_TC2_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC2_INTFLAG (SAM_TC2_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC2_STATUS (SAM_TC2_BASE+SAM_TC_STATUS_OFFSET)
-#define SAM_TC2_WAVE (SAM_TC2_BASE+SAM_TC_WAVE_OFFSET)
-#define SAM_TC2_DRVCTRL
(SAM_TC2_BASE+SAM_TC_DRVCTRL_OFFSET)
+#define SAM_TC2_WAVE (SAM_TC2_BASE+SAM_TC_WAVE_OFFSET)
+#define SAM_TC2_DRVCTRL (SAM_TC2_BASE+SAM_TC_DRVCTRL_OFFSET)
#define SAM_TC2_DBGCTRL (SAM_TC2_BASE+SAM_TC_DBGCTRL_OFFSET)
-#define SAM_TC2_SYNCBUSY (SAM_TC2_BASE+SAM_TC_SYNCBUSY_OFFSET)
+#define SAM_TC2_SYNCBUSY (SAM_TC2_BASE+SAM_TC_SYNCBUSY_OFFSET)
#define SAM_TC2_COUNT (SAM_TC2_BASE+SAM_TC_COUNT_OFFSET)
-#define SAM_TC2_COUNT8_PER
(SAM_TC2_BASE+SAM_TC_COUNT8_PER_OFFSET)
+#define SAM_TC2_COUNT8_PER (SAM_TC2_BASE+SAM_TC_COUNT8_PER_OFFSET)
#define SAM_TC2_COUNT8_CC0 (SAM_TC2_BASE+SAM_TC_COUNT8_CC0_OFFSET)
#define SAM_TC2_COUNT8_CC1 (SAM_TC2_BASE+SAM_TC_COUNT8_CC1_OFFSET)
-#define SAM_TC2_COUNT8_PERBUF
(SAM_TC2_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
-#define SAM_TC2_COUNT8_CCBUF0
(SAM_TC2_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
-#define SAM_TC2_COUNT8_CCBUF1 (SAM_TC2_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
+#define SAM_TC2_COUNT8_PERBUF
(SAM_TC2_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
+#define SAM_TC2_COUNT8_CCBUF0
(SAM_TC2_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
+#define SAM_TC2_COUNT8_CCBUF1
(SAM_TC2_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
#define SAM_TC2_COUNT16_CC0 (SAM_TC2_BASE+SAM_TC_COUNT16_CC0_OFFSET)
#define SAM_TC2_COUNT16_CC1 (SAM_TC2_BASE+SAM_TC_COUNT16_CC1_OFFSET)
-#define SAM_TC2_COUNT16_CCBUF0
(SAM_TC2_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
-#define SAM_TC2_COUNT16_CCBUF1
(SAM_TC2_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
+#define SAM_TC2_COUNT16_CCBUF0
(SAM_TC2_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
+#define SAM_TC2_COUNT16_CCBUF1
(SAM_TC2_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
#define SAM_TC2_COUNT32_CC0 (SAM_TC2_BASE+SAM_TC_COUNT32_CC0_OFFSET)
#define SAM_TC2_COUNT32_CC1 (SAM_TC2_BASE+SAM_TC_COUNT32_CC1_OFFSET)
-#define SAM_TC2_COUNT32_CCBUF0
(SAM_TC2_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
-#define SAM_TC2_COUNT32_CCBUF1
(SAM_TC2_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
+#define SAM_TC2_COUNT32_CCBUF0
(SAM_TC2_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
+#define SAM_TC2_COUNT32_CCBUF1
(SAM_TC2_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
#define SAM_TC3_CTRLA (SAM_TC3_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC3_CTRLBCLR (SAM_TC3_BASE+SAM_TC_CTRLBCLR_OFFSET)
@@ -166,25 +166,25 @@
#define SAM_TC3_INTENSET (SAM_TC3_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC3_INTFLAG (SAM_TC3_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC3_STATUS (SAM_TC3_BASE+SAM_TC_STATUS_OFFSET)
-#define SAM_TC3_WAVE (SAM_TC3_BASE+SAM_TC_WAVE_OFFSET)
-#define SAM_TC3_DRVCTRL
(SAM_TC3_BASE+SAM_TC_DRVCTRL_OFFSET)
+#define SAM_TC3_WAVE (SAM_TC3_BASE+SAM_TC_WAVE_OFFSET)
+#define SAM_TC3_DRVCTRL (SAM_TC3_BASE+SAM_TC_DRVCTRL_OFFSET)
#define SAM_TC3_DBGCTRL (SAM_TC3_BASE+SAM_TC_DBGCTRL_OFFSET)
-#define SAM_TC3_SYNCBUSY (SAM_TC3_BASE+SAM_TC_SYNCBUSY_OFFSET)
+#define SAM_TC3_SYNCBUSY (SAM_TC3_BASE+SAM_TC_SYNCBUSY_OFFSET)
#define SAM_TC3_COUNT (SAM_TC3_BASE+SAM_TC_COUNT_OFFSET)
-#define SAM_TC3_COUNT8_PER
(SAM_TC3_BASE+SAM_TC_COUNT8_PER_OFFSET)
+#define SAM_TC3_COUNT8_PER (SAM_TC3_BASE+SAM_TC_COUNT8_PER_OFFSET)
#define SAM_TC3_COUNT8_CC0 (SAM_TC3_BASE+SAM_TC_COUNT8_CC0_OFFSET)
#define SAM_TC3_COUNT8_CC1 (SAM_TC3_BASE+SAM_TC_COUNT8_CC1_OFFSET)
-#define SAM_TC3_COUNT8_PERBUF
(SAM_TC3_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
-#define SAM_TC3_COUNT8_CCBUF0
(SAM_TC3_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
-#define SAM_TC3_COUNT8_CCBUF1 (SAM_TC3_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
+#define SAM_TC3_COUNT8_PERBUF
(SAM_TC3_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
+#define SAM_TC3_COUNT8_CCBUF0
(SAM_TC3_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
+#define SAM_TC3_COUNT8_CCBUF1
(SAM_TC3_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
#define SAM_TC3_COUNT16_CC0 (SAM_TC3_BASE+SAM_TC_COUNT16_CC0_OFFSET)
#define SAM_TC3_COUNT16_CC1 (SAM_TC3_BASE+SAM_TC_COUNT16_CC1_OFFSET)
-#define SAM_TC3_COUNT16_CCBUF0
(SAM_TC3_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
-#define SAM_TC3_COUNT16_CCBUF1
(SAM_TC3_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
+#define SAM_TC3_COUNT16_CCBUF0
(SAM_TC3_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
+#define SAM_TC3_COUNT16_CCBUF1
(SAM_TC3_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
#define SAM_TC3_COUNT32_CC0 (SAM_TC3_BASE+SAM_TC_COUNT32_CC0_OFFSET)
#define SAM_TC3_COUNT32_CC1 (SAM_TC3_BASE+SAM_TC_COUNT32_CC1_OFFSET)
-#define SAM_TC3_COUNT32_CCBUF0
(SAM_TC3_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
-#define SAM_TC3_COUNT32_CCBUF1
(SAM_TC3_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
+#define SAM_TC3_COUNT32_CCBUF0
(SAM_TC3_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
+#define SAM_TC3_COUNT32_CCBUF1
(SAM_TC3_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
#define SAM_TC4_CTRLA (SAM_TC4_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC4_CTRLBCLR (SAM_TC4_BASE+SAM_TC_CTRLBCLR_OFFSET)
@@ -194,25 +194,25 @@
#define SAM_TC4_INTENSET (SAM_TC4_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC4_INTFLAG (SAM_TC4_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC4_STATUS (SAM_TC4_BASE+SAM_TC_STATUS_OFFSET)
-#define SAM_TC4_WAVE (SAM_TC4_BASE+SAM_TC_WAVE_OFFSET)
-#define SAM_TC4_DRVCTRL
(SAM_TC4_BASE+SAM_TC_DRVCTRL_OFFSET)
+#define SAM_TC4_WAVE (SAM_TC4_BASE+SAM_TC_WAVE_OFFSET)
+#define SAM_TC4_DRVCTRL (SAM_TC4_BASE+SAM_TC_DRVCTRL_OFFSET)
#define SAM_TC4_DBGCTRL (SAM_TC4_BASE+SAM_TC_DBGCTRL_OFFSET)
-#define SAM_TC4_SYNCBUSY (SAM_TC4_BASE+SAM_TC_SYNCBUSY_OFFSET)
+#define SAM_TC4_SYNCBUSY (SAM_TC4_BASE+SAM_TC_SYNCBUSY_OFFSET)
#define SAM_TC4_COUNT (SAM_TC4_BASE+SAM_TC_COUNT_OFFSET)
-#define SAM_TC4_COUNT8_PER
(SAM_TC4_BASE+SAM_TC_COUNT8_PER_OFFSET)
+#define SAM_TC4_COUNT8_PER (SAM_TC4_BASE+SAM_TC_COUNT8_PER_OFFSET)
#define SAM_TC4_COUNT8_CC0 (SAM_TC4_BASE+SAM_TC_COUNT8_CC0_OFFSET)
#define SAM_TC4_COUNT8_CC1 (SAM_TC4_BASE+SAM_TC_COUNT8_CC1_OFFSET)
-#define SAM_TC4_COUNT8_PERBUF
(SAM_TC4_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
-#define SAM_TC4_COUNT8_CCBUF0
(SAM_TC4_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
-#define SAM_TC4_COUNT8_CCBUF1 (SAM_TC4_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
+#define SAM_TC4_COUNT8_PERBUF
(SAM_TC4_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
+#define SAM_TC4_COUNT8_CCBUF0
(SAM_TC4_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
+#define SAM_TC4_COUNT8_CCBUF1
(SAM_TC4_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
#define SAM_TC4_COUNT16_CC0 (SAM_TC4_BASE+SAM_TC_COUNT16_CC0_OFFSET)
#define SAM_TC4_COUNT16_CC1 (SAM_TC4_BASE+SAM_TC_COUNT16_CC1_OFFSET)
-#define SAM_TC4_COUNT16_CCBUF0
(SAM_TC4_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
-#define SAM_TC4_COUNT16_CCBUF1
(SAM_TC4_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
+#define SAM_TC4_COUNT16_CCBUF0
(SAM_TC4_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
+#define SAM_TC4_COUNT16_CCBUF1
(SAM_TC4_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
#define SAM_TC4_COUNT32_CC0 (SAM_TC4_BASE+SAM_TC_COUNT32_CC0_OFFSET)
#define SAM_TC4_COUNT32_CC1 (SAM_TC4_BASE+SAM_TC_COUNT32_CC1_OFFSET)
-#define SAM_TC4_COUNT32_CCBUF0
(SAM_TC4_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
-#define SAM_TC4_COUNT32_CCBUF1
(SAM_TC4_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
+#define SAM_TC4_COUNT32_CCBUF0
(SAM_TC4_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
+#define SAM_TC4_COUNT32_CCBUF1
(SAM_TC4_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
#define SAM_TC5_CTRLA (SAM_TC5_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC5_CTRLBCLR (SAM_TC5_BASE+SAM_TC_CTRLBCLR_OFFSET)
@@ -222,25 +222,25 @@
#define SAM_TC5_INTENSET (SAM_TC5_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC5_INTFLAG (SAM_TC5_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC5_STATUS (SAM_TC5_BASE+SAM_TC_STATUS_OFFSET)
-#define SAM_TC5_WAVE (SAM_TC5_BASE+SAM_TC_WAVE_OFFSET)
-#define SAM_TC5_DRVCTRL
(SAM_TC5_BASE+SAM_TC_DRVCTRL_OFFSET)
+#define SAM_TC5_WAVE (SAM_TC5_BASE+SAM_TC_WAVE_OFFSET)
+#define SAM_TC5_DRVCTRL (SAM_TC5_BASE+SAM_TC_DRVCTRL_OFFSET)
#define SAM_TC5_DBGCTRL (SAM_TC5_BASE+SAM_TC_DBGCTRL_OFFSET)
-#define SAM_TC5_SYNCBUSY (SAM_TC5_BASE+SAM_TC_SYNCBUSY_OFFSET)
+#define SAM_TC5_SYNCBUSY (SAM_TC5_BASE+SAM_TC_SYNCBUSY_OFFSET)
#define SAM_TC5_COUNT (SAM_TC5_BASE+SAM_TC_COUNT_OFFSET)
-#define SAM_TC5_COUNT8_PER
(SAM_TC5_BASE+SAM_TC_COUNT8_PER_OFFSET)
+#define SAM_TC5_COUNT8_PER (SAM_TC5_BASE+SAM_TC_COUNT8_PER_OFFSET)
#define SAM_TC5_COUNT8_CC0 (SAM_TC5_BASE+SAM_TC_COUNT8_CC0_OFFSET)
#define SAM_TC5_COUNT8_CC1 (SAM_TC5_BASE+SAM_TC_COUNT8_CC1_OFFSET)
-#define SAM_TC5_COUNT8_PERBUF
(SAM_TC5_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
-#define SAM_TC5_COUNT8_CCBUF0
(SAM_TC5_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
-#define SAM_TC5_COUNT8_CCBUF1 (SAM_TC5_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
+#define SAM_TC5_COUNT8_PERBUF
(SAM_TC5_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
+#define SAM_TC5_COUNT8_CCBUF0
(SAM_TC5_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
+#define SAM_TC5_COUNT8_CCBUF1
(SAM_TC5_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
#define SAM_TC5_COUNT16_CC0 (SAM_TC5_BASE+SAM_TC_COUNT16_CC0_OFFSET)
#define SAM_TC5_COUNT16_CC1 (SAM_TC5_BASE+SAM_TC_COUNT16_CC1_OFFSET)
-#define SAM_TC5_COUNT16_CCBUF0
(SAM_TC5_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
-#define SAM_TC5_COUNT16_CCBUF1
(SAM_TC5_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
+#define SAM_TC5_COUNT16_CCBUF0
(SAM_TC5_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
+#define SAM_TC5_COUNT16_CCBUF1
(SAM_TC5_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
#define SAM_TC5_COUNT32_CC0 (SAM_TC5_BASE+SAM_TC_COUNT32_CC0_OFFSET)
#define SAM_TC5_COUNT32_CC1 (SAM_TC5_BASE+SAM_TC_COUNT32_CC1_OFFSET)
-#define SAM_TC5_COUNT32_CCBUF0
(SAM_TC5_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
-#define SAM_TC5_COUNT32_CCBUF1
(SAM_TC5_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
+#define SAM_TC5_COUNT32_CCBUF0
(SAM_TC5_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
+#define SAM_TC5_COUNT32_CCBUF1
(SAM_TC5_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
/****************************************************************************
* Not used
@@ -255,25 +255,25 @@
#define SAM_TC6_INTENSET (SAM_TC6_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC6_INTFLAG (SAM_TC6_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC6_STATUS (SAM_TC6_BASE+SAM_TC_STATUS_OFFSET)
-#define SAM_TC6_WAVE (SAM_TC6_BASE+SAM_TC_WAVE_OFFSET)
-#define SAM_TC6_DRVCTRL
(SAM_TC6_BASE+SAM_TC_DRVCTRL_OFFSET)
+#define SAM_TC6_WAVE (SAM_TC6_BASE+SAM_TC_WAVE_OFFSET)
+#define SAM_TC6_DRVCTRL (SAM_TC6_BASE+SAM_TC_DRVCTRL_OFFSET)
#define SAM_TC6_DBGCTRL (SAM_TC6_BASE+SAM_TC_DBGCTRL_OFFSET)
-#define SAM_TC6_SYNCBUSY (SAM_TC6_BASE+SAM_TC_SYNCBUSY_OFFSET)
+#define SAM_TC6_SYNCBUSY (SAM_TC6_BASE+SAM_TC_SYNCBUSY_OFFSET)
#define SAM_TC6_COUNT (SAM_TC6_BASE+SAM_TC_COUNT_OFFSET)
-#define SAM_TC6_COUNT8_PER
(SAM_TC6_BASE+SAM_TC_COUNT8_PER_OFFSET)
+#define SAM_TC6_COUNT8_PER (SAM_TC6_BASE+SAM_TC_COUNT8_PER_OFFSET)
#define SAM_TC6_COUNT8_CC0 (SAM_TC6_BASE+SAM_TC_COUNT8_CC0_OFFSET)
#define SAM_TC6_COUNT8_CC1 (SAM_TC6_BASE+SAM_TC_COUNT8_CC1_OFFSET)
-#define SAM_TC6_COUNT8_PERBUF
(SAM_TC6_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
-#define SAM_TC6_COUNT8_CCBUF0
(SAM_TC6_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
-#define SAM_TC6_COUNT8_CCBUF1 (SAM_TC6_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
+#define SAM_TC6_COUNT8_PERBUF
(SAM_TC6_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
+#define SAM_TC6_COUNT8_CCBUF0
(SAM_TC6_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
+#define SAM_TC6_COUNT8_CCBUF1
(SAM_TC6_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
#define SAM_TC6_COUNT16_CC0 (SAM_TC6_BASE+SAM_TC_COUNT16_CC0_OFFSET)
#define SAM_TC6_COUNT16_CC1 (SAM_TC6_BASE+SAM_TC_COUNT16_CC1_OFFSET)
-#define SAM_TC6_COUNT16_CCBUF0
(SAM_TC6_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
-#define SAM_TC6_COUNT16_CCBUF1
(SAM_TC6_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
+#define SAM_TC6_COUNT16_CCBUF0
(SAM_TC6_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
+#define SAM_TC6_COUNT16_CCBUF1
(SAM_TC6_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
#define SAM_TC6_COUNT32_CC0 (SAM_TC6_BASE+SAM_TC_COUNT32_CC0_OFFSET)
#define SAM_TC6_COUNT32_CC1 (SAM_TC6_BASE+SAM_TC_COUNT32_CC1_OFFSET)
-#define SAM_TC6_COUNT32_CCBUF0
(SAM_TC6_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
-#define SAM_TC6_COUNT32_CCBUF1
(SAM_TC6_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
+#define SAM_TC6_COUNT32_CCBUF0
(SAM_TC6_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
+#define SAM_TC6_COUNT32_CCBUF1
(SAM_TC6_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
#define SAM_TC7_CTRLA (SAM_TC7_BASE+SAM_TC_CTRLA_OFFSET)
#define SAM_TC7_CTRLBCLR (SAM_TC7_BASE+SAM_TC_CTRLBCLR_OFFSET)
@@ -283,25 +283,25 @@
#define SAM_TC7_INTENSET (SAM_TC7_BASE+SAM_TC_INTENSET_OFFSET)
#define SAM_TC7_INTFLAG (SAM_TC7_BASE+SAM_TC_INTFLAG_OFFSET)
#define SAM_TC7_STATUS (SAM_TC7_BASE+SAM_TC_STATUS_OFFSET)
-#define SAM_TC7_WAVE (SAM_TC7_BASE+SAM_TC_WAVE_OFFSET)
-#define SAM_TC7_DRVCTRL
(SAM_TC7_BASE+SAM_TC_DRVCTRL_OFFSET)
+#define SAM_TC7_WAVE (SAM_TC7_BASE+SAM_TC_WAVE_OFFSET)
+#define SAM_TC7_DRVCTRL (SAM_TC7_BASE+SAM_TC_DRVCTRL_OFFSET)
#define SAM_TC7_DBGCTRL (SAM_TC7_BASE+SAM_TC_DBGCTRL_OFFSET)
-#define SAM_TC7_SYNCBUSY (SAM_TC7_BASE+SAM_TC_SYNCBUSY_OFFSET)
+#define SAM_TC7_SYNCBUSY (SAM_TC7_BASE+SAM_TC_SYNCBUSY_OFFSET)
#define SAM_TC7_COUNT (SAM_TC7_BASE+SAM_TC_COUNT_OFFSET)
-#define SAM_TC7_COUNT8_PER
(SAM_TC7_BASE+SAM_TC_COUNT8_PER_OFFSET)
+#define SAM_TC7_COUNT8_PER (SAM_TC7_BASE+SAM_TC_COUNT8_PER_OFFSET)
#define SAM_TC7_COUNT8_CC0 (SAM_TC7_BASE+SAM_TC_COUNT8_CC0_OFFSET)
#define SAM_TC7_COUNT8_CC1 (SAM_TC7_BASE+SAM_TC_COUNT8_CC1_OFFSET)
-#define SAM_TC7_COUNT8_PERBUF
(SAM_TC7_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
-#define SAM_TC7_COUNT8_CCBUF0
(SAM_TC7_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
-#define SAM_TC7_COUNT8_CCBUF1 (SAM_TC7_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
+#define SAM_TC7_COUNT8_PERBUF
(SAM_TC7_BASE+SAM_TC_COUNT8_PERBUF_OFFSET)
+#define SAM_TC7_COUNT8_CCBUF0
(SAM_TC7_BASE+SAM_TC_COUNT8_CCBUF0_OFFSET)
+#define SAM_TC7_COUNT8_CCBUF1
(SAM_TC7_BASE+SAM_TC_COUNT8_CCBUF1_OFFSET)
#define SAM_TC7_COUNT16_CC0 (SAM_TC7_BASE+SAM_TC_COUNT16_CC0_OFFSET)
#define SAM_TC7_COUNT16_CC1 (SAM_TC7_BASE+SAM_TC_COUNT16_CC1_OFFSET)
-#define SAM_TC7_COUNT16_CCBUF0
(SAM_TC7_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
-#define SAM_TC7_COUNT16_CCBUF1
(SAM_TC7_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
+#define SAM_TC7_COUNT16_CCBUF0
(SAM_TC7_BASE+SAM_TC_COUNT16_CCBUF0_OFFSET)
+#define SAM_TC7_COUNT16_CCBUF1
(SAM_TC7_BASE+SAM_TC_COUNT16_CCBUF1_OFFSET)
#define SAM_TC7_COUNT32_CC0 (SAM_TC7_BASE+SAM_TC_COUNT32_CC0_OFFSET)
#define SAM_TC7_COUNT32_CC1 (SAM_TC7_BASE+SAM_TC_COUNT32_CC1_OFFSET)
-#define SAM_TC7_COUNT32_CCBUF0
(SAM_TC7_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
-#define SAM_TC7_COUNT32_CCBUF1
(SAM_TC7_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
+#define SAM_TC7_COUNT32_CCBUF0
(SAM_TC7_BASE+SAM_TC_COUNT32_CCBUF0_OFFSET)
+#define SAM_TC7_COUNT32_CCBUF1
(SAM_TC7_BASE+SAM_TC_COUNT32_CCBUF1_OFFSET)
****************************************************************************/
@@ -314,7 +314,7 @@
#define TC_CTRLA_DISABLE (0 << 1) /* Bit 1: Disable */
#define TC_CTRLA_MODE_SHIFT (2)
#define TC_CTRLA_MODE_MASK (3 << TC_CTRLA_MODE_SHIFT)
-#define TC_CTRLA_MODE_COUNT16 (0 << TC_CTRLA_MODE_SHIFT)
+#define TC_CTRLA_MODE_COUNT16 (0 << TC_CTRLA_MODE_SHIFT)
#define TC_CTRLA_MODE_COUNT8 (1 << TC_CTRLA_MODE_SHIFT)
#define TC_CTRLA_MODE_COUNT32 (2 << TC_CTRLA_MODE_SHIFT)
#define TC_CTRLA_PRESCSYNC_SHIFT (4)
@@ -327,7 +327,7 @@
#define TC_CTRLA_PRESCALER_SHIFT (8)
#define TC_CTRLA_PRESCALER_MASK (7 << TC_CTRLA_PRESCALER_SHIFT)
#define TC_CTRLA_PRESCALER(n) ((uint32_t)(n) <<
TC_CTRLA_PRESCALER_SHIFT)
-#define TC_CTRLA_PRESCALER_DIV1 (0 << TC_CTRLA_PRESCALER_SHIFT)
+#define TC_CTRLA_PRESCALER_DIV1 (0 << TC_CTRLA_PRESCALER_SHIFT)
#define TC_CTRLA_PRESCALER_DIV2 (1 << TC_CTRLA_PRESCALER_SHIFT)
#define TC_CTRLA_PRESCALER_DIV4 (2 << TC_CTRLA_PRESCALER_SHIFT)
#define TC_CTRLA_PRESCALER_DIV8 (3 << TC_CTRLA_PRESCALER_SHIFT)
@@ -335,7 +335,7 @@
#define TC_CTRLA_PRESCALER_DIV64 (5 << TC_CTRLA_PRESCALER_SHIFT)
#define TC_CTRLA_PRESCALER_DIV256 (6 << TC_CTRLA_PRESCALER_SHIFT)
#define TC_CTRLA_PRESCALER_DIV1024 (7 << TC_CTRLA_PRESCALER_SHIFT)
-#define TC_CTRLA_ALOCK (1 << 11)
+#define TC_CTRLA_ALOCK (1 << 11)
#define TC_CTRLA_CAPTEN0_SHIFT (16) /* (TC_CTRLA) Capture
Channel 0 Enable */
#define TC_CTRLA_CAPTEN0 (1 << TC_CTRLA_CAPTEN0_SHIFT)
#define TC_CTRLA_CAPTEN1_SHIFT (17) /* (TC_CTRLA) Capture
Channel 1 Enable */
diff --git a/arch/arm/src/samd5e5/sam_port.h b/arch/arm/src/samd5e5/sam_port.h
index ef219a70e9..bf22451c04 100644
--- a/arch/arm/src/samd5e5/sam_port.h
+++ b/arch/arm/src/samd5e5/sam_port.h
@@ -70,13 +70,13 @@
* Peripheral: MM.. .... .... .... .... ....
*/
-#define PORT_MODE_SHIFT (22)
/* Bits 22-23: PORT mode */
+#define PORT_MODE_SHIFT (22) /* Bits 22-23: PORT mode */
#define PORT_MODE_MASK (3 << PORT_MODE_SHIFT)
# define PORT_INPUT (0 << PORT_MODE_SHIFT) /* PORT Input */
# define PORT_OUTPUT (1 << PORT_MODE_SHIFT) /* PORT Output */
# define PORT_PERIPHERAL (2 << PORT_MODE_SHIFT) /* Controlled by
peripheral */
# define PORT_INTERRUPT (3 << PORT_MODE_SHIFT) /* Interrupting
input */
-#define PORT_MODE(n) ((uint8_t)(n) << PORT_MODE_SHIFT)
+#define PORT_MODE(n) ((uint8_t)(n) << PORT_MODE_SHIFT)
/* Pull-up/down resistor control for inputs
*
diff --git a/arch/arm/src/stm32/hardware/stm32_rng.h
b/arch/arm/src/stm32/hardware/stm32_rng.h
index fb29558291..4e04597ed0 100644
--- a/arch/arm/src/stm32/hardware/stm32_rng.h
+++ b/arch/arm/src/stm32/hardware/stm32_rng.h
@@ -48,8 +48,8 @@
/* RNG Control Register */
-#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */
-#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */
+#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */
+#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */
/* RNG Status Register */
@@ -59,4 +59,4 @@
#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt
status */
#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt
status */
-#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */
diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap_legacy.h
b/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap_legacy.h
index e02ef9c8d6..bb181484ec 100644
--- a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap_legacy.h
+++ b/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap_legacy.h
@@ -155,7 +155,7 @@
/* MCO */
-#define GPIO_MCO
(GPIO_ALT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_MCO
(GPIO_ALT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
/* SPI */
diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h
b/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h
index c7054c3115..19f8d0b915 100644
--- a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h
@@ -232,7 +232,7 @@
/* MCO */
-#define GPIO_MCO_0
(GPIO_ALT|GPIO_AF0|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_MCO_0
(GPIO_ALT|GPIO_AF0|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
/* SPI */
diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap_legacy.h
b/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap_legacy.h
index 433b4193bc..75b18bb81e 100644
--- a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap_legacy.h
+++ b/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap_legacy.h
@@ -232,7 +232,7 @@
/* MCO */
-#define GPIO_MCO
(GPIO_ALT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_MCO
(GPIO_ALT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
/* SPI */
diff --git a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
index e2f932beb2..9b2e8efb0b 100644
--- a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
@@ -36,8 +36,8 @@
/* Register Offsets *********************************************************/
-#define STM32_FDCAN_CREL_OFFSET 0x0000 /* FDCAN Core Release
register */
-#define STM32_FDCAN_ENDN_OFFSET 0x0004 /* FDCAN Endian register
*/
+#define STM32_FDCAN_CREL_OFFSET 0x0000 /* FDCAN Core Release register */
+#define STM32_FDCAN_ENDN_OFFSET 0x0004 /* FDCAN Endian register */
#define STM32_FDCAN_DBTP_OFFSET 0x000C /* FDCAN Data Bit Timing &
Prescaler register */
#define STM32_FDCAN_TEST_OFFSET 0x0010 /* FDCAN Test register */
#define STM32_FDCAN_RWD_OFFSET 0x0014 /* FDCAN RAM Watchdog register */
diff --git a/arch/arm/src/stm32h7/hardware/stm32_lptim.h
b/arch/arm/src/stm32h7/hardware/stm32_lptim.h
index cae2f8e24d..5acc5b0a6d 100644
--- a/arch/arm/src/stm32h7/hardware/stm32_lptim.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_lptim.h
@@ -132,7 +132,7 @@
# define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) /* 11: 8
clocks */
#define LPTIM_CFGR_PRESC_SHIFT (9) /* Bits 9-11: Clock prescaler */
-#define LPTIM_CFGR_PRESC_MASK (7 << LPTIM_CFGR_PRESC_SHIFT)
+#define LPTIM_CFGR_PRESC_MASK (7 << LPTIM_CFGR_PRESC_SHIFT)
# define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT)
# define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT)
# define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7b3xx_flash.h
b/arch/arm/src/stm32h7/hardware/stm32h7b3xx_flash.h
index 6a53a97925..a8dbb90e74 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7b3xx_flash.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7b3xx_flash.h
@@ -130,18 +130,18 @@
# define FLASH_CR_SSN(n) ((uint32_t)((n) & 0x7f) <<
FLASH_CR_SSN_SHIFT) /* Sector n, n=0..127 */
-#define FLASH_CR_CRCEN (1 << 15)
/* Bit 15: CRC control enable */
-#define FLASH_CR_EOPIE (1 << 16)
/* Bit 16: End-of-program interrupt enable */
-#define FLASH_CR_WRPERRIE (1 << 17)
/* Bit 17: Write protection error interrupt enable */
-#define FLASH_CR_PGSERRIE (1 << 18)
/* Bit 18: Programming sequence error interrupt enable */
-#define FLASH_CR_STRBERRIE (1 << 19)
/* Bit 19: Strobe error interrupt enable */
-#define FLASH_CR_INCERRIE (1 << 21)
/* Bit 21: Inconsistency error interrupt enable */
-#define FLASH_CR_RDPERRIE (1 << 23)
/* Bit 23: Read protection error interrupt enable */
-#define FLASH_CR_RDSERRIE (1 << 24)
/* Bit 24: Secure error interrupt enable */
-#define FLASH_CR_SNECCERRIE (1 << 25)
/* Bit 25: ECC single correction error interrupt enable */
-#define FLASH_CR_DBECCERRIE (1 << 26)
/* Bit 26: ECC double detection error interrupt enable */
-#define FLASH_CR_CRCENDIE (1 << 27)
/* Bit 27: CRC end of calculation interrupt enable */
-#define FLASH_CR_CRCRDERRIE (1 << 28)
/* Bit 28: CRC read error interrupt enable bit */
+#define FLASH_CR_CRCEN (1 << 15) /* Bit
15: CRC control enable */
+#define FLASH_CR_EOPIE (1 << 16) /* Bit
16: End-of-program interrupt enable */
+#define FLASH_CR_WRPERRIE (1 << 17) /* Bit
17: Write protection error interrupt enable */
+#define FLASH_CR_PGSERRIE (1 << 18) /* Bit
18: Programming sequence error interrupt enable */
+#define FLASH_CR_STRBERRIE (1 << 19) /* Bit
19: Strobe error interrupt enable */
+#define FLASH_CR_INCERRIE (1 << 21) /* Bit
21: Inconsistency error interrupt enable */
+#define FLASH_CR_RDPERRIE (1 << 23) /* Bit
23: Read protection error interrupt enable */
+#define FLASH_CR_RDSERRIE (1 << 24) /* Bit
24: Secure error interrupt enable */
+#define FLASH_CR_SNECCERRIE (1 << 25) /* Bit
25: ECC single correction error interrupt enable */
+#define FLASH_CR_DBECCERRIE (1 << 26) /* Bit
26: ECC double detection error interrupt enable */
+#define FLASH_CR_CRCENDIE (1 << 27) /* Bit
27: CRC end of calculation interrupt enable */
+#define FLASH_CR_CRCRDERRIE (1 << 28) /* Bit
28: CRC read error interrupt enable bit */
/* Flash Status Register (SR) Bank 1 or 2 */
@@ -249,8 +249,8 @@
/* Flash Write Sector Group Protection (WPSGN) Bank 1 or 2 */
-#define FLASH_WPSGN_SHIFT (0) /* Bits 0-31: Sector
group write protection option */
-#define FLASH_WPSGN_MASK (0xffffffff <<
FLASH_WPSGN_SHIFT)
+#define FLASH_WPSGN_SHIFT (0) /* Bits 0-31: Sector group
write protection option */
+#define FLASH_WPSGN_MASK (0xffffffff << FLASH_WPSGN_SHIFT)
/* Flash Register Boot Address (BOOT) */
diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c
b/arch/arm/src/stm32h7/stm32_spi_slave.c
index 833af6703b..b35cd6d4ca 100644
--- a/arch/arm/src/stm32h7/stm32_spi_slave.c
+++ b/arch/arm/src/stm32h7/stm32_spi_slave.c
@@ -315,8 +315,8 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops =
.txch = DMAMAP_SPI##x##_TX, \
.rxsem = SEM_INITIALIZER(0), \
.txsem = SEM_INITIALIZER(0), \
- .outq = SPI_SLAVE_OUTQ(x), \
- .inq = SPI_SLAVE_INQ(x),
+ .outq = SPI_SLAVE_OUTQ(x), \
+ .inq = SPI_SLAVE_INQ(x),
#else
#define SPI_SLAVE_INIT_DMA(x)
#endif
diff --git a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c
b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c
index 88c7058ac9..f360a0b960 100644
--- a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c
+++ b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c
@@ -70,7 +70,7 @@
****************************************************************************/
#define STM32_TIM1_RES 16
-#define STM32_TIM2_RES 32
+#define STM32_TIM2_RES 32
#define STM32_TIM3_RES 16
#define STM32_TIM4_RES 16
#define STM32_TIM5_RES 32
