xiaoxiang781216 commented on code in PR #9853:
URL: https://github.com/apache/nuttx/pull/9853#discussion_r1271453000
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -284,21 +275,83 @@ config STM32U5_DCACHE1
config STM32U5_SRAM1
bool "SRAM1"
+ default y
+
+config STM32U5_SRAM2
+ bool "SRAM2"
+ default n
+
+config STM32U5_SRAM3
+ bool "SRAM3"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+config STM32U5_SRAM5
+ bool "SRAM5"
default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+comment "SRAM Options"
+
+config STM32U5_SRAM2_HEAP
+ bool "SRAM2 is used for heap"
+ default n
+ depends on STM32U5_SRAM2
+ select STM32U5_SRAM2_INIT
+ ---help---
+ The STM32U5 SRAM2 region has special properties (power,
protection, parity)
+ which may be used by the application for special purposes. But
if these
+ special properties are not needed, it may be instead added to
the heap for
+ use by malloc().
+ NOTE: you must also select an appropriate number of memory
regions in the
+ 'Memory Management' section.
+
+config STM32U5_SRAM2_INIT
+ bool "SRAM2 is initialized to zero"
+ default n
+ depends on STM32U5_SRAM2
+ ---help---
+ The STM32U5 SRAM2 region has parity checking. However, when
the system
+ powers on, the memory is in an unknown state, and reads from
uninitialized
+ memory can trigger parity faults from the random data. This
can be
+ avoided by first writing to all locations to force the parity
into a valid
+ state.
+ However, if the SRAM2 is being used for it's battery-backed
capability,
+ this may be undesirable (because it will destroy the contents).
In that
+ case, the board should handle the initialization itself at the
appropriate
+ time.
+
+config STM32U5_SRAM3_HEAP
+ bool "SRAM3 is used for heap"
+ depends on STM32U5_SRAM3
+ default n
+
+config STM32U5_SRAM5_HEAP
+ bool "SRAM5 is used for heap"
+ depends on STM32U5_SRAM5
+ default n
comment "AHB2 Peripherals"
config STM32U5_ADC1
- bool "ADC1"
- default n
+ bool "ADC1"
+ default n
config STM32U5_DCMI_PSSI
bool "DCMI_PSSI"
default n
-config STM32U5_OTG
- bool "OTG"
- default n
+config STM32U5_OTGFS
+ bool "OTG FS"
+ depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX ||
STM32U5_STM32U575XX || STM32U5_STM32U585XX
Review Comment:
space->tab
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -284,21 +275,83 @@ config STM32U5_DCACHE1
config STM32U5_SRAM1
bool "SRAM1"
+ default y
+
+config STM32U5_SRAM2
+ bool "SRAM2"
+ default n
+
+config STM32U5_SRAM3
+ bool "SRAM3"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+config STM32U5_SRAM5
+ bool "SRAM5"
default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+comment "SRAM Options"
+
+config STM32U5_SRAM2_HEAP
+ bool "SRAM2 is used for heap"
+ default n
+ depends on STM32U5_SRAM2
Review Comment:
```suggestion
depends on STM32U5_SRAM2
```
##########
arch/arm/src/stm32u5/stm32_allocateheap.c:
##########
@@ -350,6 +357,26 @@ void arm_addregion(void)
#endif /* SRAM3 */
+#ifdef CONFIG_STM32U5_SRAM5_HEAP
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+
+ /* Allow user-mode access to the SRAM5 heap */
+
+ stm32_mpu_uheap((uintptr_t)SRAM5_START, STM32_SRAM5_SIZE);
+
+#endif
+
+ /* Colorize the heap for debug */
+
+ up_heap_color((void *)SRAM5_START, STM32_SRAM5_SIZE);
Review Comment:
no change
##########
arch/arm/src/stm32u5/stm32_allocateheap.c:
##########
@@ -350,6 +357,26 @@ void arm_addregion(void)
#endif /* SRAM3 */
+#ifdef CONFIG_STM32U5_SRAM5_HEAP
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
Review Comment:
still no change
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -284,21 +275,83 @@ config STM32U5_DCACHE1
config STM32U5_SRAM1
bool "SRAM1"
+ default y
+
+config STM32U5_SRAM2
+ bool "SRAM2"
+ default n
+
+config STM32U5_SRAM3
+ bool "SRAM3"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+config STM32U5_SRAM5
+ bool "SRAM5"
default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+comment "SRAM Options"
+
+config STM32U5_SRAM2_HEAP
+ bool "SRAM2 is used for heap"
+ default n
+ depends on STM32U5_SRAM2
+ select STM32U5_SRAM2_INIT
+ ---help---
+ The STM32U5 SRAM2 region has special properties (power,
protection, parity)
+ which may be used by the application for special purposes. But
if these
+ special properties are not needed, it may be instead added to
the heap for
+ use by malloc().
+ NOTE: you must also select an appropriate number of memory
regions in the
+ 'Memory Management' section.
+
+config STM32U5_SRAM2_INIT
+ bool "SRAM2 is initialized to zero"
+ default n
+ depends on STM32U5_SRAM2
+ ---help---
+ The STM32U5 SRAM2 region has parity checking. However, when
the system
+ powers on, the memory is in an unknown state, and reads from
uninitialized
+ memory can trigger parity faults from the random data. This
can be
+ avoided by first writing to all locations to force the parity
into a valid
+ state.
+ However, if the SRAM2 is being used for it's battery-backed
capability,
+ this may be undesirable (because it will destroy the contents).
In that
+ case, the board should handle the initialization itself at the
appropriate
+ time.
+
+config STM32U5_SRAM3_HEAP
+ bool "SRAM3 is used for heap"
+ depends on STM32U5_SRAM3
+ default n
+
+config STM32U5_SRAM5_HEAP
+ bool "SRAM5 is used for heap"
+ depends on STM32U5_SRAM5
+ default n
comment "AHB2 Peripherals"
config STM32U5_ADC1
- bool "ADC1"
- default n
+ bool "ADC1"
+ default n
config STM32U5_DCMI_PSSI
bool "DCMI_PSSI"
default n
-config STM32U5_OTG
- bool "OTG"
- default n
+config STM32U5_OTGFS
+ bool "OTG FS"
+ depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX ||
STM32U5_STM32U575XX || STM32U5_STM32U585XX
+ default n
+
+config STM32U5_OTGHS
+ bool "OTG HS"
Review Comment:
ditto. I would suggest you turn on show the special char in your editor, so
you can see the difference more clear.
##########
arch/arm/src/stm32u5/Kconfig:
##########
@@ -284,21 +275,83 @@ config STM32U5_DCACHE1
config STM32U5_SRAM1
bool "SRAM1"
+ default y
+
+config STM32U5_SRAM2
+ bool "SRAM2"
+ default n
+
+config STM32U5_SRAM3
+ bool "SRAM3"
+ default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+config STM32U5_SRAM5
+ bool "SRAM5"
default n
+ depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX ||
STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \
+ STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX
+
+comment "SRAM Options"
+
+config STM32U5_SRAM2_HEAP
+ bool "SRAM2 is used for heap"
+ default n
+ depends on STM32U5_SRAM2
+ select STM32U5_SRAM2_INIT
+ ---help---
+ The STM32U5 SRAM2 region has special properties (power,
protection, parity)
+ which may be used by the application for special purposes. But
if these
+ special properties are not needed, it may be instead added to
the heap for
+ use by malloc().
+ NOTE: you must also select an appropriate number of memory
regions in the
+ 'Memory Management' section.
+
+config STM32U5_SRAM2_INIT
+ bool "SRAM2 is initialized to zero"
+ default n
+ depends on STM32U5_SRAM2
Review Comment:
ALL depends need intent by tab
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