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The following commit(s) were added to refs/heads/master by this push:
new 3341a6d2a9 Optimize stm32 RTC accuracy
3341a6d2a9 is described below
commit 3341a6d2a9e57ce82ef767bd2dc7f3ed7523d74e
Author: lpxiao <[email protected]>
AuthorDate: Mon Jul 31 21:43:15 2023 +0800
Optimize stm32 RTC accuracy
---
arch/arm/src/stm32/stm32_rtcounter.c | 51 +++++++++++++++++++-----------------
1 file changed, 27 insertions(+), 24 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_rtcounter.c
b/arch/arm/src/stm32/stm32_rtcounter.c
index 4fddcc5ec4..4ae3aeadf4 100644
--- a/arch/arm/src/stm32/stm32_rtcounter.c
+++ b/arch/arm/src/stm32/stm32_rtcounter.c
@@ -394,41 +394,44 @@ int up_rtc_initialize(void)
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
- putreg16(RTC_MAGIC, RTC_MAGIC_REG);
- }
- modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
+ modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
- /* Wait for the LSE clock to be ready */
+ /* Wait for the LSE clock to be ready */
- while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
- {
- stm32_waste();
- }
+ while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
+ {
+ stm32_waste();
+ }
- /* Select the lower power external 32,768Hz (Low-Speed External, LSE)
- * oscillator as RTC Clock Source and enable the Clock.
- */
+ /* Select the lower power external 32,768Hz (Low-Speed External, LSE)
+ * oscillator as RTC Clock Source and enable the Clock.
+ */
- modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
+ modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
- /* Enable RTC and wait for RSF */
+ /* Enable RTC and wait for RSF */
- modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
- stm32_rtc_waitlasttask();
+ modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
+ stm32_rtc_waitlasttask();
- stm32_rtc_wait4rsf();
- stm32_rtc_waitlasttask();
+ stm32_rtc_wait4rsf();
+ stm32_rtc_waitlasttask();
- /* Configure prescaler, note that these are write-only registers */
+ /* Configure prescaler, note that these are write-only registers */
- stm32_rtc_beginwr();
- putreg16(STM32_RTC_PRESCALAR_VALUE >> 16, STM32_RTC_PRLH);
- putreg16(STM32_RTC_PRESCALAR_VALUE & 0xffff, STM32_RTC_PRLL);
- stm32_rtc_endwr();
+ stm32_rtc_beginwr();
+ putreg16(STM32_RTC_PRESCALAR_VALUE >> 16, STM32_RTC_PRLH);
+ putreg16(STM32_RTC_PRESCALAR_VALUE & 0xffff, STM32_RTC_PRLL);
+ stm32_rtc_endwr();
- stm32_rtc_wait4rsf();
- stm32_rtc_waitlasttask();
+ stm32_rtc_wait4rsf();
+ stm32_rtc_waitlasttask();
+
+ /* Write the magic register after RTC initialization. */
+
+ putreg16(RTC_MAGIC, RTC_MAGIC_REG);
+ }
#ifdef CONFIG_RTC_HIRES
/* Enable overflow interrupt - alarm interrupt is enabled in
