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commit b25793ebacc6f1f90e16506f0d95c67a160d7d14 Author: Tiago Medicci Serrano <[email protected]> AuthorDate: Tue Oct 10 11:29:55 2023 -0300 esp32/spiflash: Make it similar to ESP32-S3 by removing cache state --- arch/xtensa/src/esp32/esp32_spicache.c | 18 +++- arch/xtensa/src/esp32/esp32_spicache.h | 7 +- arch/xtensa/src/esp32/esp32_spiflash.c | 119 +++++++++------------ arch/xtensa/src/esp32/esp32_spiram.c | 10 +- .../xtensa/esp32/common/scripts/legacy_sections.ld | 1 + 5 files changed, 73 insertions(+), 82 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_spicache.c b/arch/xtensa/src/esp32/esp32_spicache.c index 76bb5395ff..fe43cb6260 100644 --- a/arch/xtensa/src/esp32/esp32_spicache.c +++ b/arch/xtensa/src/esp32/esp32_spicache.c @@ -54,15 +54,25 @@ * Private Types ****************************************************************************/ +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t s_flash_op_cache_state[CONFIG_SMP_NCPUS]; + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: spiflash_disable_cache ****************************************************************************/ -void IRAM_ATTR spi_disable_cache(int cpu, uint32_t *state) +void IRAM_ATTR spi_disable_cache(int cpu) { const uint32_t cache_mask = 0x3f; /* Caches' bits in CTRL1_REG */ uint32_t regval; @@ -97,14 +107,14 @@ void IRAM_ATTR spi_disable_cache(int cpu, uint32_t *state) } #endif - *state = ret; + s_flash_op_cache_state[cpu] = ret; } /**************************************************************************** * Name: spiflash_enable_cache ****************************************************************************/ -void IRAM_ATTR spi_enable_cache(int cpu, uint32_t state) +void IRAM_ATTR spi_enable_cache(int cpu) { const uint32_t cache_mask = 0x3f; /* Caches' bits in CTRL1_REG */ uint32_t regval; @@ -133,7 +143,7 @@ void IRAM_ATTR spi_enable_cache(int cpu, uint32_t state) regval = getreg32(ctrl1reg); regval &= ~cache_mask; - regval |= state; + regval |= s_flash_op_cache_state[cpu]; putreg32(regval, ctrl1reg); } diff --git a/arch/xtensa/src/esp32/esp32_spicache.h b/arch/xtensa/src/esp32/esp32_spicache.h index 3cdd00397f..25ba86d390 100644 --- a/arch/xtensa/src/esp32/esp32_spicache.h +++ b/arch/xtensa/src/esp32/esp32_spicache.h @@ -56,14 +56,13 @@ extern "C" * * Input Parameters: * - cpu: ID of CPU to disable cache - * - state: pointer to cache reg state that will be returned * * Returned Value: - * None (the return will be over *state) + * None. * ****************************************************************************/ -void IRAM_ATTR spi_disable_cache(int cpu, uint32_t *state); +void spi_disable_cache(int cpu); /**************************************************************************** * Name: spi_enable_cache @@ -80,7 +79,7 @@ void IRAM_ATTR spi_disable_cache(int cpu, uint32_t *state); * ****************************************************************************/ -void IRAM_ATTR spi_enable_cache(int cpu, uint32_t state); +void spi_enable_cache(int cpu); #ifdef __cplusplus } diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c index 5b5d5533af..241679f0ab 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.c +++ b/arch/xtensa/src/esp32/esp32_spiflash.c @@ -65,8 +65,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Used in spiflash_cachestate_s structure even when SMP is disabled. */ - #define SPI_FLASH_WRITE_BUF_SIZE (32) #define SPI_FLASH_READ_BUF_SIZE (64) @@ -177,17 +175,6 @@ struct spiflash_map_req uint32_t page_cnt; }; -struct spiflash_cachestate_s -{ - int cpu; -#ifdef CONFIG_SMP - int other; -#endif - irqstate_t flags; - uint32_t val[CONFIG_SMP_NCPUS]; - bool sched_suspended[CONFIG_SMP_NCPUS]; -}; - #ifdef CONFIG_ESP32_SPI_FLASH_SUPPORT_PSRAM_STACK /* SPI flash work operation arguments */ @@ -233,9 +220,9 @@ static inline void spi_reset_regbits(struct esp32_spiflash_s *priv, /* Misc. helpers */ static inline void IRAM_ATTR -esp32_spiflash_opstart(struct spiflash_cachestate_s *state); +esp32_spiflash_opstart(void); static inline void IRAM_ATTR -esp32_spiflash_opdone(struct spiflash_cachestate_s *state); +esp32_spiflash_opdone(void); static bool IRAM_ATTR spiflash_pagecached(uint32_t phypage); static void IRAM_ATTR spiflash_flushmapped(size_t start, size_t size); @@ -360,6 +347,7 @@ static struct work_s g_work; static volatile bool g_flash_op_can_start = false; static volatile bool g_flash_op_complete = false; +static volatile bool g_sched_suspended[CONFIG_SMP_NCPUS]; #ifdef CONFIG_SMP static sem_t g_disable_non_iram_isr_on_core[CONFIG_SMP_NCPUS]; #endif @@ -467,31 +455,29 @@ static inline void spi_reset_regbits(struct esp32_spiflash_s *priv, * ****************************************************************************/ -static inline void IRAM_ATTR -esp32_spiflash_opstart(struct spiflash_cachestate_s *state) +static void esp32_spiflash_opstart(void) { struct tcb_s *tcb = this_task(); + int cpu = up_cpu_index(); int saved_priority = tcb->sched_priority; +#ifdef CONFIG_SMP + int other_cpu = cpu ? 0 : 1; +#endif + + DEBUGASSERT(cpu == 0 || cpu == 1); /* Temporary raise schedule priority */ nxsched_set_priority(tcb, SCHED_PRIORITY_MAX); - state->cpu = up_cpu_index(); -#ifdef CONFIG_SMP - state->other = state->cpu ? 0 : 1; -#endif - - DEBUGASSERT(state->cpu == 0 || state->cpu == 1); - #ifdef CONFIG_SMP - DEBUGASSERT(state->other == 0 || state->other == 1); - DEBUGASSERT(state->other != state->cpu); + DEBUGASSERT(other_cpu == 0 || other_cpu == 1); + DEBUGASSERT(other_cpu != cpu); if (OSINIT_OS_READY()) { g_flash_op_can_start = false; - nxsem_post(&g_disable_non_iram_isr_on_core[state->other]); + nxsem_post(&g_disable_non_iram_isr_on_core[other_cpu]); while (!g_flash_op_can_start) { @@ -502,7 +488,7 @@ esp32_spiflash_opstart(struct spiflash_cachestate_s *state) } #endif - state->sched_suspended[state->cpu] = true; + g_sched_suspended[cpu] = true; sched_lock(); @@ -510,9 +496,9 @@ esp32_spiflash_opstart(struct spiflash_cachestate_s *state) esp32_irq_noniram_disable(); - spi_disable_cache(state->cpu, &state->val[state->cpu]); + spi_disable_cache(cpu); #ifdef CONFIG_SMP - spi_disable_cache(state->other, &state->val[state->other]); + spi_disable_cache(other_cpu); #endif } @@ -524,18 +510,23 @@ esp32_spiflash_opstart(struct spiflash_cachestate_s *state) * ****************************************************************************/ -static inline void IRAM_ATTR - esp32_spiflash_opdone(struct spiflash_cachestate_s *state) +static void esp32_spiflash_opdone(void) { - DEBUGASSERT(state->cpu == 0 || state->cpu == 1); + const int cpu = up_cpu_index(); #ifdef CONFIG_SMP - DEBUGASSERT(state->other == 0 || state->other == 1); - DEBUGASSERT(state->other != state->cpu); + const int other_cpu = cpu ? 0 : 1; #endif - spi_enable_cache(state->cpu, state->val[state->cpu]); + DEBUGASSERT(cpu == 0 || cpu == 1); + #ifdef CONFIG_SMP - spi_enable_cache(state->other, state->val[state->other]); + DEBUGASSERT(other_cpu == 0 || other_cpu == 1); + DEBUGASSERT(other_cpu != cpu); +#endif + + spi_enable_cache(cpu); +#ifdef CONFIG_SMP + spi_enable_cache(other_cpu); #endif /* Signal to spi_flash_op_block_task that flash operation is complete */ @@ -546,10 +537,10 @@ static inline void IRAM_ATTR sched_unlock(); - state->sched_suspended[state->cpu] = false; + g_sched_suspended[cpu] = false; #ifdef CONFIG_SMP - while (state->sched_suspended[state->other]) + while (g_sched_suspended[other_cpu]) { /* Busy loop and wait for spi_flash_op_block_task to properly finish * and resume scheduler @@ -954,7 +945,6 @@ static int IRAM_ATTR esp32_erasesector(struct esp32_spiflash_s *priv, uint32_t addr, uint32_t size) { uint32_t offset; - struct spiflash_cachestate_s state; esp32_set_write_opt(priv); @@ -965,11 +955,11 @@ static int IRAM_ATTR esp32_erasesector(struct esp32_spiflash_s *priv, for (offset = 0; offset < size; offset += MTD_ERASESIZE(priv)) { - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); if (esp32_enable_write(priv) != OK) { - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); return -EIO; } @@ -982,16 +972,16 @@ static int IRAM_ATTR esp32_erasesector(struct esp32_spiflash_s *priv, if (esp32_wait_idle(priv) != OK) { - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); return -EIO; } - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); } - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); spiflash_flushmapped(addr, size); - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); return 0; } @@ -1094,7 +1084,6 @@ static int IRAM_ATTR esp32_writedata(struct esp32_spiflash_s *priv, uint32_t off = 0; uint32_t bytes; uint32_t tmp_buf[SPI_FLASH_WRITE_WORDS]; - struct spiflash_cachestate_s state; esp32_set_write_opt(priv); @@ -1113,9 +1102,9 @@ static int IRAM_ATTR esp32_writedata(struct esp32_spiflash_s *priv, memcpy(tmp_buf, &buffer[off], bytes); - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); ret = esp32_writeonce(priv, addr, tmp_buf, bytes); - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); if (ret) { @@ -1127,9 +1116,9 @@ static int IRAM_ATTR esp32_writedata(struct esp32_spiflash_s *priv, off += bytes; } - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); spiflash_flushmapped(addr, size); - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); return OK; } @@ -1162,7 +1151,6 @@ static int IRAM_ATTR esp32_writedata_encrypted( int blocks; int ret = OK; uint32_t tmp_buf[SPI_FLASH_ENCRYPT_WORDS]; - struct spiflash_cachestate_s state; if (addr % SPI_FLASH_ENCRYPT_UNIT_SIZE) { @@ -1184,7 +1172,7 @@ static int IRAM_ATTR esp32_writedata_encrypted( { memcpy(tmp_buf, buffer, SPI_FLASH_ENCRYPT_UNIT_SIZE); - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); esp_rom_spiflash_write_encrypted_enable(); ret = esp_rom_spiflash_prepare_encrypted_data(addr, tmp_buf); @@ -1203,22 +1191,22 @@ static int IRAM_ATTR esp32_writedata_encrypted( } esp_rom_spiflash_write_encrypted_disable(); - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); addr += SPI_FLASH_ENCRYPT_UNIT_SIZE; buffer += SPI_FLASH_ENCRYPT_UNIT_SIZE; size -= SPI_FLASH_ENCRYPT_UNIT_SIZE; } - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); spiflash_flushmapped(addr, size); - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); return 0; exit: esp_rom_spiflash_write_encrypted_disable(); - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); return ret; } @@ -1313,15 +1301,14 @@ static int IRAM_ATTR esp32_readdata(struct esp32_spiflash_s *priv, uint32_t off = 0; uint32_t bytes; uint32_t tmp_buf[SPI_FLASH_READ_WORDS]; - struct spiflash_cachestate_s state; while (size > 0) { bytes = MIN(size, SPI_FLASH_READ_BUF_SIZE); - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); ret = esp32_readonce(priv, addr, tmp_buf, bytes); - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); if (ret) { @@ -1365,10 +1352,9 @@ static int IRAM_ATTR esp32_mmap(struct esp32_spiflash_s *priv, int start_page; int flash_page; int page_cnt; - struct spiflash_cachestate_s state; bool flush = false; - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); for (start_page = DROM0_PAGES_START; start_page < DROM0_PAGES_END; @@ -1421,7 +1407,7 @@ static int IRAM_ATTR esp32_mmap(struct esp32_spiflash_s *priv, #endif } - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); return ret; } @@ -1445,9 +1431,8 @@ static void IRAM_ATTR esp32_ummap(struct esp32_spiflash_s *priv, const struct spiflash_map_req *req) { int i; - struct spiflash_cachestate_s state; - esp32_spiflash_opstart(&state); + esp32_spiflash_opstart(); for (i = req->start_page; i < req->start_page + req->page_cnt; ++i) { @@ -1464,7 +1449,7 @@ static void IRAM_ATTR esp32_ummap(struct esp32_spiflash_s *priv, #ifdef CONFIG_SMP cache_flush(1); #endif - esp32_spiflash_opdone(&state); + esp32_spiflash_opdone(); } /**************************************************************************** @@ -2409,9 +2394,7 @@ static int spi_flash_op_block_task(int argc, char *argv[]) /* Flash operation is complete, re-enable cache */ -#if 0 spi_enable_cache(cpu); -#endif /* Restore interrupts that aren't located in IRAM */ diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c index b9212bcf0f..7b62a51acd 100644 --- a/arch/xtensa/src/esp32/esp32_spiram.c +++ b/arch/xtensa/src/esp32/esp32_spiram.c @@ -84,10 +84,8 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, int psize, int num) { uint32_t regval; - uint32_t statecpu0; #ifdef CONFIG_SMP int cpu_to_stop = 0; - uint32_t statecpu1; bool smp_start = OSINIT_OS_READY(); #endif unsigned int i; @@ -184,10 +182,10 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, up_cpu_pause(cpu_to_stop); } - spi_disable_cache(1, &statecpu1); + spi_disable_cache(1); #endif - spi_disable_cache(0, &statecpu0); + spi_disable_cache(0); /* mmu change */ @@ -213,9 +211,9 @@ unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, putreg32(regval, DPORT_APP_CACHE_CTRL1_REG); } - spi_enable_cache(0, statecpu0); + spi_enable_cache(0); #ifdef CONFIG_SMP - spi_enable_cache(1, statecpu1); + spi_enable_cache(1); if (smp_start) { diff --git a/boards/xtensa/esp32/common/scripts/legacy_sections.ld b/boards/xtensa/esp32/common/scripts/legacy_sections.ld index 80eefe19b8..dab3308376 100644 --- a/boards/xtensa/esp32/common/scripts/legacy_sections.ld +++ b/boards/xtensa/esp32/common/scripts/legacy_sections.ld @@ -78,6 +78,7 @@ SECTIONS #endif *libarch.a:esp32_cpuindex.*(.literal .text .literal.* .text.*) *libarch.a:esp32_irq.*(.literal .text .literal.* .text.*) + *libarch.a:esp32_spicache.*(.literal .text .literal.* .text.*) *libarch.a:esp32_spiflash.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*)
