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The following commit(s) were added to refs/heads/master by this push:
new 9c793067cc xtensa/esp32s3: Fix esp32s3 mcuboot ota crash
9c793067cc is described below
commit 9c793067cc2a3669366a07029be17bc3b71ca11b
Author: Eren Terzioglu <[email protected]>
AuthorDate: Wed Nov 29 13:23:21 2023 +0300
xtensa/esp32s3: Fix esp32s3 mcuboot ota crash
---
.../esp32s3/common/scripts/mcuboot_sections.ld | 103 +++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
b/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
index e8cbb99b23..fd1f8e92b5 100644
--- a/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
+++ b/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
@@ -71,6 +71,13 @@ SECTIONS
*(.rodata)
*(.rodata.*)
+#ifdef CONFIG_ESP32S3_WIRELESS
+ *(.rodata_wlog_verbose.*)
+ *(.rodata_wlog_debug.*)
+ *(.rodata_wlog_info.*)
+ *(.rodata_wlog_warning.*)
+ *(.rodata_wlog_error.*)
+#endif
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
@@ -168,6 +175,74 @@ SECTIONS
*(.iram1 .iram1.*)
esp32s3_start.*(.literal .text .literal.* .text.*)
+ *libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*)
+ *libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*)
+ *libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*)
+ *libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
+
+#ifdef CONFIG_ESP32S3_BLE
+ *libc.a:sq_remlast.*(.literal .text .literal.* .text.*)
+#endif
+
+ *libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*)
+
+ *libsched.a:assert.*(.literal .text .literal.* .text.*)
+ *libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
+ *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
+ *libsched.a:irq_spinlock.*(.literal .text .literal.* .text.*)
+ *libsched.a:sched_note.*(.literal .text .literal.* .text.*)
+ *libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
+ *libsched.a:sched_thistask.*(.literal .text .literal.* .text.*)
+ *libsched.a:spinlock.*(.literal .text .literal.* .text.*)
+
+#ifdef CONFIG_ESP32S3_SPEED_UP_ISR
+ *libarch.a:xtensa_switchcontext.*(.literal.up_switch_context
.text.up_switch_context)
+
+ *libarch.a:esp32s3_timerisr.*(.literal.systimer_isr .text.systimer_isr)
+ *libarch.a:esp32s3_idle.*(.literal.up_idle .text.up_idle)
+ *libarch.a:esp32s3_dma.*(.literal.esp32s3_dma_load .text.esp32s3_dma_load \
+ .literal.esp32s3_dma_enable
.text.esp32s3_dma_enable)
+
+ *libsched.a:sched_processtimer.*(.literal.nxsched_process_timer
.text.nxsched_process_timer)
+ *libsched.a:clock_initialize.*(.literal.clock_timer .text.clock_timer)
+ *libsched.a:wd_start.*(.literal.wd_timer .text.wd_timer)
+ *libsched.a:sched_roundrobin.*(.literal.nxsched_process_roundrobin
.text.nxsched_process_roundrobin)
+ *libsched.a:sched_reprioritizertr.*(.literal.nxsched_reprioritize_rtr
.text.nxsched_reprioritize_rtr)
+ *libsched.a:sched_removereadytorun.*(.literal.nxsched_remove_readytorun
.text.nxsched_remove_readytorun)
+ *libsched.a:sched_addreadytorun.*(.literal.nxsched_add_readytorun
.text.nxsched_add_readytorun)
+ *libsched.a:sched_addprioritized.*(.literal.nxsched_add_prioritized
.text.nxsched_add_prioritized)
+ *libsched.a:sched_mergepending.*(.literal.nxsched_merge_pending
.text.nxsched_merge_pending)
+ *libsched.a:sched_resumescheduler.*(.literal.nxsched_resume_scheduler
.text.nxsched_resume_scheduler)
+
+ *libc.a:sq_remfirst.*(.literal.sq_remfirst .text.sq_remfirst)
+#endif
+
+ *libarch.a:esp32s3_spi_timing.*(.literal .text .literal.* .text.*)
+#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD
+ *libarch.a:esp32s3_psram_quad.*(.literal .text .literal.* .text.*)
+#endif
+#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT
+ *libarch.a:esp32s3_psram_octal.*(.literal .text .literal.* .text.*)
+#endif
+#if defined(CONFIG_STACK_CANARIES) && \
+ (defined(CONFIG_ESP32S3_SPIFLASH) || \
+ defined(CONFIG_ESP32S3_SPIRAM))
+ *libc.a:lib_stackchk.*(.literal .text .literal.* .text.*)
+#endif
+
+ *(.wifirxiram .wifirxiram.*)
+ *(.wifi0iram .wifi0iram.*)
+ *(.wifiorslpiram .wifiorslpiram.*)
+ *(.wifislpiram .wifislpiram.*)
+ *(.wifislprxiram .wifislprxiram.*)
+ *(.phyiram .phyiram.*)
+
/* align + add 16B for CPU dummy speculative instr. fetch */
. = ALIGN(4) + 16;
@@ -242,6 +317,15 @@ SECTIONS
KEEP (*(.jcr))
*(.dram1 .dram1.*)
esp32s3_start.*(.rodata .rodata.*)
+
+ *libphy.a:(.rodata .rodata.*)
+ *libarch.a:xtensa_context.*(.rodata .rodata.*)
+#if defined(CONFIG_STACK_CANARIES) && \
+ (defined(CONFIG_ESP32S3_SPIFLASH) || \
+ defined(CONFIG_ESP32S3_SPIRAM))
+ *libc.a:lib_stackchk.*(.rodata .rodata.*)
+#endif
+
_edata = ABSOLUTE(.);
. = ALIGN(4);
@@ -263,6 +347,25 @@ SECTIONS
_iram_end = ABSOLUTE(.);
} >iram0_0_seg
+ .iram0.data :
+ {
+ . = ALIGN(4);
+
+ *(.iram.data)
+ *(.iram.data.*)
+ } >iram0_0_seg
+
+ .iram0.bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+
+ *(.iram.bss)
+ *(.iram.bss.*)
+
+ . = ALIGN(4);
+ _iram_end = ABSOLUTE(.);
+ } >iram0_0_seg
+
_image_irom_vma = ADDR(.flash.text);
_image_irom_lma = LOADADDR(.flash.text);
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) -
_image_irom_lma;
