Updated Branches: refs/heads/master fe640a253 -> 9ae8bfaf1
TS-1212 can not limit ram cache, also fix the stats the may not the root cause, but we should have fixed the stats. set RECP_NON_PERSISTENT on ram_cache.total_bytes we should not force int on int64_t, in CACHE_VOL_SUM_DYN_STAT and other micros with help from Wei Jin, thanks Project: http://git-wip-us.apache.org/repos/asf/trafficserver/repo Commit: http://git-wip-us.apache.org/repos/asf/trafficserver/commit/9ae8bfaf Tree: http://git-wip-us.apache.org/repos/asf/trafficserver/tree/9ae8bfaf Diff: http://git-wip-us.apache.org/repos/asf/trafficserver/diff/9ae8bfaf Branch: refs/heads/master Commit: 9ae8bfaf17709f4629cb1a376590e7b829e3f12c Parents: fe640a2 Author: Zhao Yongming <[email protected]> Authored: Fri Apr 20 13:49:26 2012 +0800 Committer: Zhao Yongming <[email protected]> Committed: Tue Apr 24 14:45:39 2012 +0800 ---------------------------------------------------------------------- CHANGES | 2 ++ iocore/cache/Cache.cc | 28 +++++++++++++--------------- iocore/cache/P_CacheInternal.h | 10 +++++----- 3 files changed, 20 insertions(+), 20 deletions(-) ---------------------------------------------------------------------- http://git-wip-us.apache.org/repos/asf/trafficserver/blob/9ae8bfaf/CHANGES ---------------------------------------------------------------------- diff --git a/CHANGES b/CHANGES index 839016d..e8be231 100644 --- a/CHANGES +++ b/CHANGES @@ -1,5 +1,7 @@ -*- coding: utf-8 -*- Changes with Apache Traffic Server 3.1.4 + *) [TS-1212] can not limit ram cache, also fix the stats. + *) [TS-1214] another race condition in cache init. *) [TS-1130] Wrong CAS operation on ink_time_t on 64 bit system. http://git-wip-us.apache.org/repos/asf/trafficserver/blob/9ae8bfaf/iocore/cache/Cache.cc ---------------------------------------------------------------------- diff --git a/iocore/cache/Cache.cc b/iocore/cache/Cache.cc index 06eff9e..78ef360 100644 --- a/iocore/cache/Cache.cc +++ b/iocore/cache/Cache.cc @@ -721,10 +721,10 @@ CacheProcessor::cacheInitialized() int cache_init_ok = 0; /* allocate ram size in proportion to the disk space the volume accupies */ - int64_t total_size = 0; - uint64_t total_cache_bytes = 0; - uint64_t total_direntries = 0; - uint64_t used_direntries = 0; + int64_t total_size = 0; // count in HTTP & MIXT + uint64_t total_cache_bytes = 0; // bytes that can used in total_size + uint64_t total_direntries = 0; // all the direntries in the cache + uint64_t used_direntries = 0; // and used uint64_t vol_total_cache_bytes = 0; uint64_t vol_total_direntries = 0; uint64_t vol_used_direntries = 0; @@ -770,6 +770,7 @@ CacheProcessor::cacheInitialized() (unsigned int) caches_ready, gnvol); int64_t ram_cache_bytes = 0; if (gnvol) { + // new ram_caches, with algorithm from the config for (i = 0; i < gnvol; i++) { switch (cache_config_ram_cache_algorithm) { default: @@ -781,6 +782,7 @@ CacheProcessor::cacheInitialized() break; } } + // let us cocalate the Size if (cache_config_ram_cache_size == AUTO_SIZE_RAM_CACHE) { Debug("cache_init", "CacheProcessor::cacheInitialized - cache_config_ram_cache_size == AUTO_SIZE_RAM_CACHE"); for (i = 0; i < gnvol; i++) { @@ -789,12 +791,8 @@ CacheProcessor::cacheInitialized() ram_cache_bytes += vol_dirlen(gvol[i]); Debug("cache_init", "CacheProcessor::cacheInitialized - ram_cache_bytes = %" PRId64 " = %" PRId64 "Mb", ram_cache_bytes, ram_cache_bytes / (1024 * 1024)); - /* - CACHE_VOL_SUM_DYN_STAT(cache_ram_cache_bytes_total_stat, - (int64_t)vol_dirlen(gvol[i])); - */ - RecSetGlobalRawStatSum(vol->cache_vol->vol_rsb, - cache_ram_cache_bytes_total_stat, (int64_t) vol_dirlen(gvol[i])); + CACHE_VOL_SUM_DYN_STAT(cache_ram_cache_bytes_total_stat, (int64_t) vol_dirlen(gvol[i])); + vol_total_cache_bytes = gvol[i]->len - vol_dirlen(gvol[i]); total_cache_bytes += vol_total_cache_bytes; Debug("cache_init", "CacheProcessor::cacheInitialized - total_cache_bytes = %" PRId64 " = %" PRId64 "Mb", @@ -814,6 +812,9 @@ CacheProcessor::cacheInitialized() } } else { + // we got configured memory size + // TODO, should we check the available system memories, or you will + // OOM or swapout, that is not a good situation for the server Debug("cache_init", "CacheProcessor::cacheInitialized - %" PRId64 " != AUTO_SIZE_RAM_CACHE", cache_config_ram_cache_size); int64_t http_ram_cache_size = @@ -1776,7 +1777,7 @@ int Cache::open(bool clear, bool fix) { NOWARN_UNUSED(fix); int i; - off_t blocks; + off_t blocks = 0; cache_read_done = 0; total_initialized_vol = 0; total_nvol = 0; @@ -2591,14 +2592,11 @@ static void reg_int(const char *str, int stat, RecRawStatBlock *rsb, const char void register_cache_stats(RecRawStatBlock *rsb, const char *prefix) { - char stat_str[256]; - // Special case for this sucker, since it uses its own aggregator. reg_int("bytes_used", cache_bytes_used_stat, rsb, prefix, cache_stats_bytes_used_cb); REG_INT("bytes_total", cache_bytes_total_stat); - snprintf(stat_str, sizeof(stat_str), "%s.%s", prefix, "ram_cache.total_bytes"); - RecRegisterRawStat(rsb, RECT_PROCESS, stat_str, RECD_INT, RECP_NULL, (int) cache_ram_cache_bytes_total_stat, RecRawStatSyncSum); + REG_INT("ram_cache.total_bytes", cache_ram_cache_bytes_total_stat); REG_INT("ram_cache.bytes_used", cache_ram_cache_bytes_stat); REG_INT("ram_cache.hits", cache_ram_cache_hits_stat); REG_INT("ram_cache.misses", cache_ram_cache_misses_stat); http://git-wip-us.apache.org/repos/asf/trafficserver/blob/9ae8bfaf/iocore/cache/P_CacheInternal.h ---------------------------------------------------------------------- diff --git a/iocore/cache/P_CacheInternal.h b/iocore/cache/P_CacheInternal.h index 9244bd3..075bb00 100644 --- a/iocore/cache/P_CacheInternal.h +++ b/iocore/cache/P_CacheInternal.h @@ -180,15 +180,15 @@ extern RecRawStatBlock *cache_rsb; RecIncrRawStat(vol->cache_vol->vol_rsb, mutex->thread_holding, (int) (x), -1); #define CACHE_VOL_SUM_DYN_STAT(x,y) \ - RecIncrRawStat(vol->cache_vol->vol_rsb, mutex->thread_holding, (int) (x), (int) y); + RecIncrRawStat(vol->cache_vol->vol_rsb, mutex->thread_holding, (int) (x), (int64_t) y); #define CACHE_SUM_DYN_STAT(x, y) \ - RecIncrRawStat(cache_rsb, mutex->thread_holding, (int) (x), (int) (y)); \ - RecIncrRawStat(vol->cache_vol->vol_rsb, mutex->thread_holding, (int) (x), (int) (y)); + RecIncrRawStat(cache_rsb, mutex->thread_holding, (int) (x), (int64_t) (y)); \ + RecIncrRawStat(vol->cache_vol->vol_rsb, mutex->thread_holding, (int) (x), (int64_t) (y)); #define CACHE_SUM_DYN_STAT_THREAD(x, y) \ - RecIncrRawStat(cache_rsb, this_ethread(), (int) (x), (int) (y)); \ - RecIncrRawStat(vol->cache_vol->vol_rsb, this_ethread(), (int) (x), (int) (y)); + RecIncrRawStat(cache_rsb, this_ethread(), (int) (x), (int64_t) (y)); \ + RecIncrRawStat(vol->cache_vol->vol_rsb, this_ethread(), (int) (x), (int64_t) (y)); #define GLOBAL_CACHE_SUM_GLOBAL_DYN_STAT(x, y) \ RecIncrGlobalRawStatSum(cache_rsb,(x),(y))
