This is an automated email from the ASF dual-hosted git repository.
tqchen pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-tvm-vta.git.
at 37e05a1 [CI] Setup VTA CI
This branch includes the following new commits:
new 669a59f Initial commit
new 6b0a4e4 hardware compilation flow, and driver tests
new 948b3fd doxygen path update
new 49bea25 [DOCS] Initial docs (#4)
new ca54f03 [REFACTOR] Code base refactoring (#5)
new e7557db [REFACTOR] Macro standardization, lint tests (#7)
new 16b5877 [PYTHON, TVM] Python TVM library, unit tests and end to end
example
new 3da38f5 fixing URL; adding () to print (#17)
new 981559c Upgrade TVM to latest version
new d69472e [RPC][RUNTIME] Support dynamic reload of runtime API
according to config (#19)
new 1f7c859 [SCHEDULER, HW] Auto scheduler for conv2d, hardware
generation (#20)
new 0e8a1d3 [COMPILER] Refactor compiler to enable configuration (#21)
new 374be00 [DRIVER][RUNTIME] Make runtime fully device agnostic (#23)
new 59f6eef [DRIVER] Add simulator, unify testcase to unittest (#25)
new f44efa0 [RUNTIME] Simplify dynamic library and code path. (#27)
new cfaed3d [INFRASTRUCTURE] Migrate to json based config. Move gemm test
to integration. (#28)
new df374cf Refactor, refactor code structure, fix pynq rpc (#29)
new 9dcfe0a [TEST] CI infrastructure (#30)
new bf7472c fix jenkins (#31)
new 71c0f82 [COMPILER] Upgrade to meet latest TVM IR pragma convention
(#32)
new 726e047 [PYTHON] Enable environment scoping (#33)
new 08e4bd5 [HARDWARE, TEST] Fixed hardware generation flow (#34)
new 56f21f6 [TOPI] Automated schedule in conv2d TOPI lib, moving to GEMM
intrinsic (#35)
new 2494787 Update Graph Support for Batching, Fix Swapping (#37)
new aa40347 [BITSTREAM SERVER] Bitstream server integration (#38)
new 25c7039 [INIT] Allow proper throw in compiler (#39)
new c6c45f6 [EXAMPLE] Fix example for simulator (#40)
new 074e430 [DOC, EXAMPLE] Updated READMEs, tests, etc. (#41)
new da3568a VTA and TVM on PYTHONPATH, also pass to sudo (#42)
new 013dd45 Update TVM Version and CI scripts (#46)
new 270e9be Update Jenkinsfile
new 8641bf5 [DOC] VTA installation & basic tutorials (#47)
new 4f79ec9 [UTILS, DOC] Use TVM file downloading utility, conv2d
tutorial (#48)
new 4e035be [DOCKER] Cleanup docker image (#50)
new 404bf26 [DOC, TVM] ResNet tutorial, updated TVM (#51)
new 27c8b6f [TVM] Upgrade TVM Support
new 32dc7f0 [NNVM] Make param file python version agnostic
new 9c9a165 [TUTORIAL] Resnet-18 end to end tutorial example (#55)
new ea9e519 [TOPI] Fix the CPU op perf (#56)
new d5d1f74 [BUILD][DOCS] Migrate VTA CI, test, build, docs
new 1bf7d24 [DOCS] VTA installation guide (#1428)
new a7df108 Update VTA schedule (#1464)
new 978c739 [DOC, HARDWARE] Hardware developer guide, migrating to use
Vivado 2018.2 (#1473)
new f8a36c6 [IR] support general type annotation. (#1480)
new 1c4dfbb [DOC] Update VTA readme files to avoid stale information
(#1484)
new 3e974cc timing closure fix for default VTA config (#1489)
new 53748b6 [NNVM] Fix check in layout parsing (#1502)
new d54df27 [VTA] bugfix parameter derivation (#1521)
new 43ce06b [AUTOTVM] TOPI integration for ARM CPU (#1487)
new 7159d47 [AUTOTVM] Simplify TopHub (#1630)
new 5840887 Remove leading "./" from include paths (#1640)
new 3af21a6 [SUBMODULE] update submodule to latest (#1728)
new 8dac6f5 Fix VTA Tutorial for more strict graphrt check (#1737)
new 51ea5c7 [DOC]Errors corrected (#1767)
new 400a742 [RUNTIME] Add fp16/fp32 conversion functions (#1766)
new 6500bb3 [VTA] pynq v2.1 -> v2.3 (#1945)
new 9ab4128 [TOPI] Specify non-zero absolute tolerance in tests (#1925)
new 0fc5812 [TOPI] Add dilation argument to conv2d and depthwise_conv2d
(#1970)
new 9bef80c [VTA] Improved RPC for VTA (#2043)
new 417a562 [RELAY][EXPR] Make const numpy consistent (#2349)
new 43110a8 Optimize Linux shared library modules (*.so files) (#2445)
new 45fdee0 Misc refactor on graph runtime, layout node (#2557)
new 282c063 [TUTORIAL] Fix downloaded file path (#2590)
new 5c49b07 Fix pylint 2.2.2 gripes. (#2642)
new f088ab3 Stop pylint complaining about useless import alias. (#2655)
new 01f1246 [HEADER] Add Header to Comply with ASF Release Policy (#2982)
new 58f070f [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware
Simulation for VTA #3009 (#3010)
new 08c4c3f [BugFix][VTA] Fix bug in vta runtime DepPop function. (#3208)
new 5c5f57b [VTA] [TSIM] Improve tsim example (#3206)
new 7b92c80 [VTA][TSIM] Use Module instead of RawModule for testbench by
creating an empty bundle for the IO (#3242)
new 302637c [BugFix][VTA] Fix vta_conv2d crash issue after change
vta_config.json configuration. (#3213)
new 3c23363 [Bugfix][VTA] PkgConfig cause crash in PYNQ board due to link
library (#3257)
new fbd494d [Bugfix] [VTA] VTA DRAM Have A Logic Issue May Cause GEMM
Output Wrong. (#3278)
new 2f24e4a [VTA] [Hardware] Chisel implementation (#3258)
new da299fc [VTA] [APPS] [TSIM] small naming fix (#3293)
new 30b183e [VTA] add doc to tsim-example driver and update verilator env
variable (#3302)
new fa0aa6c [VTA] [APPS] [TSIM] update documentation (README) (#3318)
new 82686b9 add another default location to verilator (#3324)
new c5ebbe7 [VTA][TSIM] update app example (#3343)
new 91026e7 [VTA] add support to event counters (#3347)
new 453b73c fix hardware-makefile for osx, bugfix chisel-RegFile, and
rename driver (#3371)
new 3455ef3 [VTA] Fix VTA function Vivado Compile Error. (#3375)
new 1ac6213 [VTA] [APPS] Update README on tsim example (#3409)
new 5d228cf [VTA] Add VTA PYNQ metal_test bitstream program logic and fix
compile issue. (#3400)
new 0816033 [VTA][TSIM] Verilator compile report error for printf (#3438)
new dacd7b6 [VTA][Relay] Relay Compilation + AutoTVM compatible operator
libraries for VTA (#3135)
new 669aa86 Clean up pass.h (#3312)
new 4b85cbe producing simulation statistics instead of time to get useful
information out of simulation runs (#3481)
new 33b2f06 [VTA][Hotfix] Avoiding error when environment variable is not
set (#3497)
new 1cad4c6 [relay][frontend] Return Module from get_workload (#3483)
new b01a87b [VTA] TSIM improvements and fixes (#3505)
new a836413 Fix pylint issue in vta/python/vta/top/graphpack.py (#3519)
new 2d42612 fix pynq 32-bit address pointers (#3558)
new 5f3f2b6 avoiding cast None to int errors (#3578)
new 5b6eb69 bugfix function args order in alu instruction generation
(#3592)
new 8a27e11 add coherent, length, and user bits option to Shell Config
(#3593)
new 6c41083 [VTA] Runtime refactor to allow for non-shared memory FPGAs
(e.g. F1) (#3554)
new 2aad7f3 remove tabs (#3603)
new 7b0123f [VTA] [Chisel] support for different inp/wgt bits, rewrote
DotProduct for clarity (#3605)
new c9ac0c2 [VTA] [Chisel] fix tensor issue/commit in gemm (#3637)
new aacd35a fix case when offset is odd and size is even (#3643)
new 0917860 fix comment/doc in TensorLoad (#3646)
new dd4ca23 [VTA] Refactor to increase platform coverage (Ultra96 etc.)
(#3496)
new 5bff873 [VTA] [Chisel] make dram offset configurable for uops
different than 4-bytes (#3654)
new cffabb0 removing deprecated script (#3667)
new 255d9b2 [VTA] Support for batched inference (#3661)
new 3563047 [VTA] VTA Compilation Script for Intel FPGA (#3494)
new 436d23b [VTA] [Chisel] Added Chisel Module Unit Test Infrastructure
(#3698)
new c3894cb safe to remove thread related headers? (#3713)
new b18c28d [VTA][Dockerfile] Chisel dependencies for TSIM CI (#3721)
new 4241739 [VTA] [Chisel] Bug fix for VME Shell (#3737)
new fc9ae85 [VTA] [Chisel] Improved Data Gen, Added ALU Test (#3743)
new 5c7868a [VTA][TSIM][Build] Towards TSIM CI testing (#3704)
new 0c7843c [VTA][Chisel] run all unittests by default (#3766)
new 64459d6 syntax fix (#3765)
new d022b73 fix dense tuning (#3768)
new f46cb55 [VTA][Chisel] scale dram base address in hardware instead of
runtime (#3772)
new 1a207bf [VTA][TSIM] parallel TSIM hardware compilation with macOS and
debug support (#3797)
new 9eff1d2 [VTA][TSIM] Introduce Virtual Memory for TSIM Driver (#3686)
new ef5a7d0 [VTA] Parameterization and bug fix in TensorLoad module
(#3841)
new a3049d0 [VTA] Fix RewriteForceSerial Function logic issue. (#3854)
new d441887 [VTA][TSIM] add virtual memory support to tsim example (#3868)
new 8fe1c05 [VTA][Chisel] rename USE_TSIM macro with USE_VTA64 and
cleanup runtime (#3872)
new 43a353c [VTA] Fix TSIM compile error in Linux (add missing -fPIC
flag) (#3876)
new 6e9e970 [VTA][Chisel] add scalafmt and format existing scala codebase
(#3880)
new db39351 [VTA][Chisel] add ISA BitPat generation (#3891)
new 94311b3 [VTA] de10-nano driver (#3394)
new 51e9742 [VTA][Relay] Extending Vision model coverage compilation for
VTA (#3740)
new 29a0e9a [VTA][TOPI] Conv2d transpose (deconvolution) operator support
(#3777)
new cb9958a [VTA] Support TLPP in function simulator. (#3555)
new 32dbf8e [VTA][Config] hotfix denano10 (#3918)
new 9b58279 [VTA] RPC path update. (#3924)
new 89be933 [ARITH] cleanup the indexmod/div on python side (#4028)
new 94354d6 Fix wrong n_trial number in autotvm tutorials' progress bar
(#4070)
new 6e0dbee [VTA][TSIM] Serial GEMM Application Added (#4082)
new 5b1350f TensorCore Support using Intrinsic (#4136)
new 0b53071 [VTA][Chisel] TSIM VTA Source Refactor (#4163)
new bc133b9 [VTA] Performance optimize, remove unnecessary contigious
memory use. (#4246)
new 476a09c [DOCS] Update link loc (#4257)
new 2ad49d2 [VTA] Hotfix for padded load test in Chisel VTA (#4264)
new 834ddf1 [RUNTIME][REFACTOR] Use object protocol to support
runtime::Module (#4289)
new 779d39d fix error when memory_id is VTA_MEM_ID_OUT (#4330)
new 4416086 [VTA] Bug fix for padded load with large inputs (#4293)
new c09ec7d [SOURCE] Add ASF header to __init__.py files (#4359)
new 8b69697 update_document_after_repository_renamed (#4398)
new d1494bc [Release] resolve license issues (#4408)
new 365b03b [LINT] Remove unnecessary copyright message for files with
ASF header (#4409)
new 84db548 [License] move cma_api to 3rdparty. separate BSD 2-clause and
3-clause (#4410)
new cdffa81 removing nnvm dep from VTA sources (#4419)
new 31a0082 [VTA][HotFix] Relay->VTA quantization fix (#4433)
new c78802e [VTA] Enable streamlined GEMM execution (#4392)
new 2a35023 fix multiple transfer issue in loaduop (#4442)
new 639b9e9 [VTA] Bringing group convolution support (#4421)
new 81327ed [VTA] Speedup TSIM by Multi-threading (#4491)
new 919681d fix crash issue in tsim backend (#4527)
new f99f4ef [VTA] improved virtual memory mapping (#4545)
new 4e30e95 [VTA][Chisel] End-to-end Inference with Chisel VTA (#4574)
new b693922 [VTA] Throw exception on mis-formatted files and avoid
overwrite Scala code (#4555)
new 80f518a Added declare of aluBits for TensorAlu (#4624)
new 453d0c8 [REFACTOR][IR] Introduce SeqStmt to replace ir::Block (#4627)
new 7ffd5c5 Pin python pillow to "<7" due to torchvision 1.2.0 dependency
issue (#4632)
new 3667499 [Relay][TOPI]Fix meaning of conv2d_transpose output_padding
parameter (#4318)
new 9d7a962 [VTA] Fix an issue in updating uop_idx in the TensorGemm
module (#4694)
new e7e5f79 Revert "[Relay][TOPI]Fix meaning of conv2d_transpose
output_padding parameter (#4318)" (#4708)
new 57f9d7f [REFACTOR][FFI] Make more clear naming for C API Type codes.
(#4715)
new 6bb74c0 [VTA][TSIM] Enable TSIM CI Testing (#4407)
new 3a669d6 [REFACTOR][CODEGEN] codegen->target, build_module->driver
(#4742)
new 01ed0cd [VTA] Support network which have no unique operator as
start/stop name for graph pack. (#4703)
new 81dc28d [LINT] Fix -Wextra (#4804)
new d60fb1c [DOCS] Fix vta tutorial (#4809)
new 076cacb [REFACTOR][PY][API-Change] Polish tvm.runtime,
tvm.runtime.module API update (#4837)
new 2614c30 [Doc][AutoTVM] Fix bugs that override n_trials (#4842)
new 651bdc4 [LINT][PY] Fixes for pylint==2.4.4 (#4849)
new 36e08ac [REFACTOR][PY][API-CHANGE] establish tvm.ir, migrate
corresponding files (#4862)
new a38b851 [REFACTOR][PY][API-CHANGE] Establish tvm.target
new 8bf06c3 [REFACTOR][PY] Establish tvm.tir
new 8558e4e [REFACTOR][PY] Establish tvm.te and tvm.driver (#4900)
new 17fe773 [REFACTOR][PY] Establish tvm.arith (#4904)
new 2753b8b [DOCS] Fix Sphinx Warnings (RST indent, cross-ref, and image
scale) (#4920)
new 7fa68ba [Relay][AutoTVM] Relay op strategy (#4644)
new 436850f [DOCS] Fix Sphinx Warning: the target found for
cross-reference (#4925)
new bbe20bb [VTA] YoloV3 Support (#4887)
new 23657d2 [REFACTOR][PY][API-CHANGE] Remove legacy python files. (#4943)
new 28958c6 [DOCS] Sphinx -- Introduce alias detection. (#4954)
new 495428c [VTA][Chisel] Change Scala Linter scalafmt => scalastyle
(#4998)
new 164f3e0 [VTA][Chisel,de10nano] Chisel fixes and de10nano support
(#4986)
new 38da791 [VTA] VTA hardware/software codebase re-org (#5037)
new 40f7116 [Autotvm] Fix autotvm customized template (#5034)
new 66223ef [TUTORIAL] Fix vta tutorial after relay function refactor
(#5095)
new 48fa54b [VTA][Refactor] Introducing VTA_HW_PATH for easier migration
(#5163)
new 36828b8 [BUILD] Fix VTA build in CI (#5165)
new ed30d7b License notice
new b097f01 [REFACTOR] VTA-HW setup
new 37e05a1 [CI] Setup VTA CI
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