tqchen commented on code in PR #17665: URL: https://github.com/apache/tvm/pull/17665#discussion_r1961785106
########## python/tvm/tir/build.py: ########## @@ -0,0 +1,557 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. + +# pylint: disable=invalid-name +"""The build utils in python.""" +from typing import Union, Optional, Dict, Tuple +import enum +import tvm +from tvm import tir, ir +from tvm.runtime import ndarray +from tvm.tir import PrimFunc +from tvm.ir.module import IRModule +from tvm.target import Target +from tvm._ffi.runtime_ctypes import Device + + +def create_pass_list(disable_loop_partition: bool): + """Create a list of passes based on pass context configurations. + + Parameters + ---------- + disable_loop_partition : bool + Whether to disable loop partition pass. + + Returns + ------- + List[tvm.tir.transform.Pass] + List of passes to run. + """ + pass_ctx = tvm.transform.PassContext.current() + config = pass_ctx.config + # Retrieve configuration flags. + disable_vectorize = bool(config.get("tir.disable_vectorize", False)) + disable_storage_rewrite = bool(config.get("tir.disable_storage_rewrite", False)) + instrument_bound_checkers = bool(config.get("tir.instrument_bound_checkers", False)) + disable_cse_tir = bool(config.get("tir.disable_cse_tir", False)) + enable_equiv_terms_in_cse_tir = bool(config.get("tir.enable_equiv_terms_in_cse_tir", False)) + ptx_ldg32 = bool(config.get("tir.ptx_ldg32", False)) + instrument_lwp = bool(config.get("tir.instrument_lwp", False)) + add_lower_pass = config.get("tir.add_lower_pass", []) + + # Group user passes by phase (phases 0, 1, 2, and 3 where phase>=3 goes to 3) + user_passes = {0: [], 1: [], 2: [], 3: []} + for phase, p in add_lower_pass: + if not isinstance(phase, int) or phase < 0: + raise ValueError( + f"Phase number must be a non-negative integer, got {phase} of type {type(phase)}" + ) + user_passes[phase if phase < 3 else 3].append(p) + + # Construct phase-specific passes. + phase0 = user_passes[0] + + phase1 = [ + tir.transform.InjectPrefetch(), + tir.transform.TextureFlatten(), + tir.transform.StorageFlatten(64, instrument_bound_checkers), + tir.transform.LowerCrossThreadReduction(), + tir.transform.LowerInitBlock(), + tir.transform.PlanAndUpdateBufferAllocationLocation(), + tir.transform.ConvertBlocksToOpaque(), + tir.transform.LiftThreadBinding(), + tir.transform.ManifestSharedMemoryLocalStage(), + tir.transform.CompactBufferAllocation(), + tir.transform.LowerAutoCopy(), + tir.transform.UnifyThreadBinding(), + tir.transform.LowerMatchBuffer(), + tir.transform.Simplify(), + tir.transform.InjectPermutedLayout(), + tir.transform.Simplify(), + tir.transform.InjectSoftwarePipeline(), + tir.transform.TransformMmaBufferLayout(), + tir.transform.LowerOpaqueBlock(), + tir.transform.FlattenBuffer(), + tir.transform.BF16ComputeLegalize(), + tir.transform.NarrowDataType(32), + tir.transform.Simplify(), Review Comment: change this phase to to lower_tir_pases -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
