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new beca091e36 [LLVM] Fix JIT unknown reloc issue for case of RISCV
beca091e36 is described below
commit beca091e36948dc7258a4f7c93d6c71db83cb1c7
Author: Balint Cristian <[email protected]>
AuthorDate: Mon May 12 18:13:44 2025 +0300
[LLVM] Fix JIT unknown reloc issue for case of RISCV
---
src/target/llvm/llvm_instance.cc | 55 +++++++++---------------------
src/target/llvm/llvm_module.cc | 6 ++++
tests/python/target/test_riscv_features.py | 22 +++++-------
3 files changed, 31 insertions(+), 52 deletions(-)
diff --git a/src/target/llvm/llvm_instance.cc b/src/target/llvm/llvm_instance.cc
index 6efbb296d9..ebf9a754b1 100644
--- a/src/target/llvm/llvm_instance.cc
+++ b/src/target/llvm/llvm_instance.cc
@@ -53,18 +53,6 @@
#include <llvm/Support/raw_ostream.h>
#include <llvm/Target/TargetMachine.h>
#include <llvm/Target/TargetOptions.h>
-#if TVM_LLVM_VERSION >= 190
-#include <llvm/TargetParser/RISCVISAInfo.h>
-#else
-#if TVM_LLVM_VERSION >= 140
-#include <llvm/Support/RISCVISAInfo.h>
-#endif
-#endif
-#if TVM_LLVM_VERSION >= 160
-#include <llvm/TargetParser/RISCVTargetParser.h>
-#else
-#include <llvm/Support/TargetParser.h>
-#endif
#include <tvm/ffi/container/array.h>
#include <tvm/ffi/container/map.h>
#include <tvm/ffi/optional.h>
@@ -299,34 +287,25 @@ LLVMTargetInfo::LLVMTargetInfo(LLVMInstance& instance,
const TargetJSON& target)
// code model
code_model_ = llvm::CodeModel::Medium;
#if TVM_LLVM_VERSION >= 140
- // VLEN inference
- const auto cpu_name =
GetOrCreateTargetMachine(false)->getMCSubtargetInfo()->getCPU();
- const auto canon_arch = llvm::RISCV::getMArchFromMcpu(cpu_name);
- auto ISAInfo =
- llvm::RISCVISAInfo::parseArchString(canon_arch,
/*EnableExperimentalExtensions=*/true);
- // infer VLEN from LLVM RISCVInfo parser
- if (!llvm::errorToBool(ISAInfo.takeError()) && (vector_width_ == 0)) {
- vector_width_ = (*ISAInfo)->getMinVLen();
- }
- // infer VLEN from LLVM options (zvlXXXb override)
- for (const auto& attr : attrs_) {
- if (attr.find("zvl") != std::string::npos) {
- std::string vec;
- for (char c : attr) {
- if (std::isdigit(c)) vec += c;
+ // get VLEN from the LLVM backend (zvlXXXb)
+ Map<String, String> features = GetAllLLVMCpuFeatures();
+ // check vector ISA
+ if (features.count("v") > 0) {
+ vector_width_ = 0;
+ int zvlbits = 0;
+ for (const auto& [attr, val] : features) {
+ if (std::string(attr).find("zvl") != std::string::npos) {
+ std::string vec;
+ for (char c : std::string(attr)) {
+ if (std::isdigit(c)) vec += c;
+ }
+ zvlbits = std::stoi(vec);
+ // max of the multiple zvlXXXb
+ if (vector_width_ < zvlbits) vector_width_ = zvlbits;
}
- vector_width_ = std::stoi(vec);
}
}
#endif
- if (vector_width_ > 0) {
- // push cl-opt to LLVM
- llvm_options_.push_back(
- ParseOptionString("-riscv-v-vector-bits-min:int=" +
std::to_string(vector_width_)));
- } else {
- // fallback default (codegen will warn)
-
llvm_options_.push_back(ParseOptionString("-riscv-v-vector-bits-min:int=256"));
- }
}
// Target options
@@ -943,9 +922,7 @@ const int LLVMTargetInfo::GetVectorWidth() {
} else if (arch == llvm::Triple::arm || arch == llvm::Triple::aarch64) {
vector_width_ = 128;
} else if (arch == llvm::Triple::riscv32 || arch == llvm::Triple::riscv64)
{
- vector_width_ = 256;
- LOG(WARNING) << "LLVM RVV VLEN inference failed, "
- << "using 256 bits, set -vector-width=XXX to override";
+ vector_width_ = 128;
} else {
// fallback default
vector_width_ = 128;
diff --git a/src/target/llvm/llvm_module.cc b/src/target/llvm/llvm_module.cc
index db8961de30..e8bfc9f19e 100644
--- a/src/target/llvm/llvm_module.cc
+++ b/src/target/llvm/llvm_module.cc
@@ -31,8 +31,10 @@
#include <llvm/ExecutionEngine/MCJIT.h>
#include <llvm/ExecutionEngine/Orc/LLJIT.h>
#include <llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h>
+#if _WIN32
#include <llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h>
#include <llvm/ExecutionEngine/SectionMemoryManager.h>
+#endif
#include <llvm/IR/DataLayout.h>
#include <llvm/IR/Function.h>
#include <llvm/IR/Intrinsics.h>
@@ -503,9 +505,13 @@ void LLVMModuleNode::InitORCJIT() {
const auto linkerBuilder =
[&](llvm::orc::ExecutionSession& session,
const llvm::Triple& triple) ->
std::unique_ptr<llvm::orc::ObjectLayer> {
+#if _WIN32
auto GetMemMgr = []() { return
std::make_unique<llvm::SectionMemoryManager>(); };
auto ObjLinkingLayer =
std::make_unique<llvm::orc::RTDyldObjectLinkingLayer>(session,
std::move(GetMemMgr));
+#else
+ auto ObjLinkingLayer =
std::make_unique<llvm::orc::ObjectLinkingLayer>(session);
+#endif
if (triple.isOSBinFormatCOFF()) {
ObjLinkingLayer->setOverrideObjectFlagsWithResponsibilityFlags(true);
ObjLinkingLayer->setAutoClaimResponsibilityForObjectSymbols(true);
diff --git a/tests/python/target/test_riscv_features.py
b/tests/python/target/test_riscv_features.py
index 765d492a2d..17452a86db 100644
--- a/tests/python/target/test_riscv_features.py
+++ b/tests/python/target/test_riscv_features.py
@@ -24,20 +24,16 @@ LLVM_VERSION = codegen.llvm_version_major()
# fmt: off
min_llvm_version, tvm_target, vec_width = tvm.testing.parameters(
- # generic, no-vec -> (default 256)
- (-1, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+i,+m", 256),
- (-1, "llvm -device=riscv_cpu -mtriple=riscv32-linux-gnu -mcpu=generic-rv32
-mattr=+64bit,+a,+c,+d,+f,+m", 256),
- # generic, with-vec -> (default 256)
- (-1, "llvm -device=riscv_cpu -mtriple=riscv32-linux-gnu -mcpu=generic-rv32
-mattr=+i,+m,+v", 256),
- (-1, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+64bit,+a,+c,+d,+f,+m,+v", 256),
- # explicit -vector-width
- (-1, "llvm -device=riscv_cpu -vector-width=128 -mtriple=riscv32-linux-gnu
-mcpu=generic-rv32 -mattr=+i,+m,+v", 128),
- (-1, "llvm -device=riscv_cpu -vector-width=128 -mtriple=riscv64-linux-gnu
-mcpu=generic-rv64 -mattr=+64bit,+a,+c,+d,+f,+m,+v", 128),
- (-1, "llvm -device=riscv_cpu -vector-width=512 -mtriple=riscv32-linux-gnu
-mcpu=generic-rv32 -mattr=+i,+m,+v", 512),
- (-1, "llvm -device=riscv_cpu -vector-width=512 -mtriple=riscv64-linux-gnu
-mcpu=generic-rv64 -mattr=+64bit,+a,+c,+d,+f,+m,+v", 512),
+ # generic, no vector -> (default 128)
+ (-1, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+i,+m", 128),
+ (-1, "llvm -device=riscv_cpu -mtriple=riscv32-linux-gnu -mcpu=generic-rv32
-mattr=+64bit,+a,+c,+d,+f,+m", 128),
+ # generic, with vector -> (default zvl128b)
+ (-1, "llvm -device=riscv_cpu -mtriple=riscv32-linux-gnu -mcpu=generic-rv32
-mattr=+i,+m,+v", 128),
+ (-1, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+64bit,+a,+c,+d,+f,+m,+v", 128),
# explicit +zvlXXXb
- (14, "llvm -device=riscv_cpu -mtriple=riscv32-linux-gnu -mcpu=generic-rv32
-mattr=+i,+m,+v,+zvl64b", 64),
- (14, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+64bit,+a,+c,+d,+f,+m,+v,+zvl64b", 64),
+ (14, "llvm -device=riscv_cpu -mtriple=riscv32-linux-gnu -mcpu=generic-rv32
-mattr=+i,+m,+v,+zvl64b", 128),
+ (14, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+64bit,+a,+c,+d,+f,+m,+v,+zvl256b", 256),
+ (14, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu -mcpu=generic-rv64
-mattr=+64bit,+a,+c,+d,+f,+m,+v,+zvl512b", 512),
# vendor CPU
(17, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu
-mcpu=sifive-x280", 512),
(18, "llvm -device=riscv_cpu -mtriple=riscv64-linux-gnu
-mcpu=sifive-p670", 128),
