(tvm) branch main updated: [Target][RISC-V] Use riscv_cpu device key for RISC-V target tags (#19915)

[tqchen]

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The following commit(s) were added to refs/heads/main by this push:
     new 9e8cfea358 [Target][RISC-V] Use riscv_cpu device key for RISC-V target 
tags (#19915)
9e8cfea358 is described below

commit 9e8cfea3585089daa10b197fd7282dff75c0edbc
Author: Qize Li <2864630...@qq.com>
AuthorDate: Tue Jun 30 23:18:24 2026 +0800

    [Target][RISC-V] Use riscv_cpu device key for RISC-V target tags (#19915)
    
    RISC-V target tags use the LLVM codegen backend, so their target kind
    should remain "llvm". However, the target metadata should still identify
    the target as a RISC-V CPU rather than an ARM CPU.
    
    Previously, the RISC-V tag helper used the ARM CPU keys and device
    metadata, so Target("riscv/...") expanded with keys ["arm_cpu", "cpu"]
    and device "arm_cpu".
    
    ```python
    {"kind": "llvm", "keys": ["arm_cpu", "cpu"], "device": "arm_cpu"}
    ```
    
    This is misleading for code that inspects target keys or device metadata
    to distinguish CPU families.
    
    This change updates the RISC-V tag helper to use keys ["riscv_cpu",
    "cpu"] and device "riscv_cpu", while keeping kind="llvm". It also adds
    the SpacemiT K3 RISC-V target tag.
---
 python/tvm/target/tag_registry/riscv_cpu.py | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/python/tvm/target/tag_registry/riscv_cpu.py 
b/python/tvm/target/tag_registry/riscv_cpu.py
index 3b5fc95d40..b1d5c50da9 100644
--- a/python/tvm/target/tag_registry/riscv_cpu.py
+++ b/python/tvm/target/tag_registry/riscv_cpu.py
@@ -20,7 +20,7 @@ from .registry import register_tag
 
 
 def _register_riscv_tag(name, config):
-    base = {"kind": "llvm", "keys": ["arm_cpu", "cpu"], "device": "arm_cpu"}
+    base = {"kind": "llvm", "keys": ["riscv_cpu", "cpu"], "device": 
"riscv_cpu"}
     base.update(config)
     register_tag(name, base)
 
@@ -71,3 +71,14 @@ _register_riscv_tag(
         "mabi": "lp64d",
     },
 )
+
+_register_riscv_tag(
+    "riscv/spacemit-k3",
+    {
+        "num-cores": 8,
+        "mtriple": "riscv64-unknown-linux-gnu",
+        "mcpu": "spacemit-x100",
+        "mfloat-abi": "hard",
+        "mabi": "lp64d",
+    },
+)