giuseros commented on a change in pull request #5754:
URL: https://github.com/apache/incubator-tvm/pull/5754#discussion_r443699271
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File path: python/tvm/relay/qnn/op/legalizations.py
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@@ -237,17 +237,23 @@ def is_fast_int8_on_arm():
target = tvm.target.Target.current(allow_none=False)
return '+v8.2a,+dotprod' in ' '.join(target.options)
+def is_aarch64_arm():
+ """ Checks whether we are compiling for an AArch64 target. """
+ target = tvm.target.Target.current(allow_none=False)
+ return 'aarch64' in ' '.join(target.options)
+
########################
# ARM CPU legalizations.
########################
@qnn_conv2d_legalize.register('arm_cpu')
def _qnn_conv2d_legalize_arm_cpu(attrs, inputs, types):
# ARM prefers the dtypes to be same.
- if is_fast_int8_on_arm():
+ if (is_aarch64_arm() and attrs["data_layout"] == "NHWC") or
is_fast_int8_on_arm():
Review comment:
Well, that condition is there so that all AArch32 and NCHW will follow
the original path (convert to int16, subtract offsets contributions, and then
convolve). I would prefer to have it this way to affect the minimum the
code-base.
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