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liuyizhi pushed a commit to branch v0.6
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The following commit(s) were added to refs/heads/v0.6 by this push:
new 26807ba [BACKPORT-0.6][VTA] End-to-end Inference with Chisel VTA
(#5896)
26807ba is described below
commit 26807bac800cb3ba2658c9ee33980abd4ca5d9b6
Author: Liangfu Chen <[email protected]>
AuthorDate: Thu Jun 25 12:28:40 2020 +0800
[BACKPORT-0.6][VTA] End-to-end Inference with Chisel VTA (#5896)
* [BACKPORT-0.6][VTA][Chisel] End-to-end Inference with Chisel VTA (#4574)
* [BACKPORT-0.6][VTA] Added declare of aluBits for TensorAlu (#4624)
Co-authored-by: Kevin Yuan <[email protected]>
* retrigger ci
* retrigger ci
Co-authored-by: Kevin Yuan <[email protected]>
---
vta/hardware/chisel/src/main/scala/core/TensorAlu.scala | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
index b438641..21e57f2 100644
--- a/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
+++ b/vta/hardware/chisel/src/main/scala/core/TensorAlu.scala
@@ -108,6 +108,7 @@ class AluVector(implicit p: Parameters) extends Module {
* acc-scratchpad.
*/
class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module
{
+ val aluBits = p(CoreKey).accBits
val io = IO(new Bundle {
val start = Input(Bool())
val done = Output(Bool())
@@ -230,7 +231,8 @@ class TensorAlu(debug: Boolean = false)(implicit p:
Parameters) extends Module {
tensorImm.data.valid := state === sReadTensorB
tensorImm.data.bits.foreach { b =>
b.foreach { c =>
- c := dec.alu_imm
+ c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1),
+ Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm),
dec.alu_imm)
}
}