remotego commented on a change in pull request #9:
URL: https://github.com/apache/incubator-tvm-vta/pull/9#discussion_r456738642
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File path: config/intelfocl_sample.json
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@@ -0,0 +1,13 @@
+{
+ "TARGET" : "intelfocl",
Review comment:
I believe "Arria 10" is too restrictive here. The code should work for
all devices supported by Intel OpenCL for FPGA, namely Arria 10, Stratix V/10
and Cyclone V/10. That's the reason we name it as "intelfocl".
So far we have tested it on both Arria 10 and Stratix 10 boards, and it
worked for both boards.
The correct bitstream will be generated automatically according to the
card/BSP/toolchain installed on the system. For example, if you have a Stratix
10 card and toolchain(BSP) installed on your system, the bitstream generated
will work on your Stratix 10 card.
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