vegaluisjose commented on pull request #6126: URL: https://github.com/apache/tvm/pull/6126#issuecomment-782729723
If the instruction layout changed, then definitely the [ISA](https://github.com/apache/tvm-vta/blob/main/hardware/chisel/src/main/scala/core/ISA.scala) and [Decode](https://github.com/apache/tvm-vta/blob/main/hardware/chisel/src/main/scala/core/Decode.scala) module have to be updated accordingly. Chisel Bundles, used to decode the instructions, are pretty similar to the C-struct used in the vta-hardware-spec to define instructions. The WIDTHs for instruction field are defined in the ISA module. Hope it helps! ---------------------------------------------------------------- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: [email protected]
