zhanghaohit commented on pull request #6126: URL: https://github.com/apache/tvm/pull/6126#issuecomment-791252853
> If the instruction layout changed, then definitely the [ISA](https://github.com/apache/tvm-vta/blob/main/hardware/chisel/src/main/scala/core/ISA.scala) and [Decode](https://github.com/apache/tvm-vta/blob/main/hardware/chisel/src/main/scala/core/Decode.scala) module have to be updated accordingly. > > Chisel Bundles, used to decode the instructions, are pretty similar to the C-struct used in the vta-hardware-spec to define instructions. The WIDTHs for instruction field are defined in the ISA module. > > Hope it helps! Thanks @vegaluisjose for the suggestion. I'm wondering if it is possible to let Chisel derive parameters from the hardware_params.h so that we do not have to modify two different places when ISA changes? I tried to reflect the changes that I made in [hardware_params.h](https://github.com/apache/tvm-vta/commit/3806c7d32ea0df0a55637c14d0d06610efbd4181#diff-88c6ef8abd0669a09ed73cad6feeab902e792901dd0c9e0b58d2f7d3bb25f29dR121) onto Chisel, but still not manage to make it work. I think it is not an easy 1-to-1 mapping task, and it takes some time to understand the definitions in Chisel. ---------------------------------------------------------------- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. For queries about this service, please contact Infrastructure at: [email protected]
