stevenmburns commented on pull request #27:
URL: https://github.com/apache/tvm-vta/pull/27#issuecomment-854920693
@adavare I'm not completely following what you are doing here but if you
aren't changing the scratchpad interface from the original design, you'll need
to make one modification in LoadUop (delay the LSB by the same amount as the
synchronous read).
```
when(io.vme_rd.data.fire()) {
mem.write(waddr, wdata, wmask)
}
// read-from-sram
io.uop.data.valid := RegNext(io.uop.idx.valid)
// delay LSB of idx by a cycle because of the one-cycle memory read latency
val sIdx = RegNext(io.uop.idx.bits % numUop.U)
val rIdx = io.uop.idx.bits >> log2Ceil(numUop)
val memRead = mem.read(rIdx, io.uop.idx.valid)
val sWord = memRead.asUInt.asTypeOf(wdata)
val sUop = sWord(sIdx).asTypeOf(io.uop.data.bits)
io.uop.data.bits <> sUop
```
If you are inserting our new TensorLoad implementation in this PR, then we
corrected that in there.
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