Lunderberg opened a new pull request #12: URL: https://github.com/apache/tvm-rfcs/pull/12
I put this together following [TVM PR#8528](https://github.com/apache/tvm/pull/8528), which resolved an issue with array access in the Vulkan runtime, but led to/exposed some inconsistencies in the TIR semantics for buffer indices. Vulkan/SPIR-V require all arrays to be typed, and doesn't allow type casts that would be permissible in C code, such as casting between `float32*` and `float32x2*`. As a result, any vectorized load/store operations must act on an array whose elements are vectorized types. Currently, many places in IR (e.g. [`Load::Load`](https://github.com/apache/tvm/blob/07243a89/src/tir/ir/expr.cc#L621) checking the number of output lanes) and codegen (e.g. [`CodeGenC`'s `LoadNode`](https://github.com/apache/tvm/blob/07243a89/src/target/source/codegen_c.cc#L719) loop over output lanes rather than element/index lanes) implicitly assume that all array elements have `lanes == 1`. I couldn't find any documentation on intended semantics for these multi-lane array indices, and so I wanted to propose, discuss, and document the intended semantics. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
