huajsj commented on a change in pull request #14: URL: https://github.com/apache/tvm-rfcs/pull/14#discussion_r683080499
########## File path: rfcs/0012-pipeline-executor.md ########## @@ -0,0 +1,367 @@ +<!--- Licensed to the Apache Software Foundation (ASF) under one --> +<!--- or more contributor license agreements. See the NOTICE file --> +<!--- distributed with this work for additional information --> +<!--- regarding copyright ownership. The ASF licenses this file --> +<!--- to you under the Apache License, Version 2.0 (the --> +<!--- "License"); you may not use this file except in compliance --> +<!--- with the License. You may obtain a copy of the License at --> + +<!--- http://www.apache.org/licenses/LICENSE-2.0 --> + +<!--- Unless required by applicable law or agreed to in writing, --> +<!--- software distributed under the License is distributed on an --> +<!--- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY --> +<!--- KIND, either express or implied. See the License for the --> +<!--- specific language governing permissions and limitations --> +<!--- under the License. --> +- Feature Name: (fill me in with a unique identifier, `my_awesome_feature`) +- Start Date: (fill me in with today's date, YYYY-MM-DD) +- RFC PR: [apache/tvm-rfcs#0014](https://github.com/apache/tvm-rfcs/pull/0014) +- GitHub Issue: [apache/tvm#8596](https://github.com/apache/tvm/issues/8596) + +## 1. Summary + + +This proposal introduces Pipeline Executor: A runtime executor that by scheduling +splitted subgraph of relay graph in pipeline to implement task level parallism to +reduce compute latency. + +## 2. Motivation + + + +Currently more and more edge device inference deployment cases happens on SOC device, +SOC device have heterogenous chipset like GPU, FPGA, CPU, DSP…, to reach the best +performance there is a requirement to run the ML network parallel in these heterogenous +chipset, however currently graph executor solution only doing the serialize operator +execution without papalism logic and the existing data papalism solution only support +parallel on same chipset(device), then only way to do batch processing on heterogenous +device with tvm is that treat whole ML network as schedule unit and running them on +different heterogenous device but that would cause latency issue(low speed chipset +generate big latency for single data processing) . + +Therefore, we need an runtime executor that can provide papalism scheduling function +with a smaller schedule unit like subgraph (a group of operator with dependency relation) +to be more efficient to use SOC heterogenous hardware resource and get better performance. + + +### Benefits of Pipeline Executor + +There are three benefit for Pipeline Executor + +Pipeline Executor provides: +* Compute single network on Multiple backend in parallel to improve performance. Review comment: for example for a resnet18 compute, first we manually split the network into 4 subgraph, then use pipeline executor to build these four subgraph with target llvm+cpu(0), opencl-gpu(0), opencl -gpu(1), VTA(FPGA), and generate the dependency relation, when pipeline executor run the compute, the resnet18(now already get split into 4 subgraph) would get running in multiple backend in parallel(pipeline). -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
