PhilippvK commented on issue #10141: URL: https://github.com/apache/tvm/issues/10141#issuecomment-1038014042
I've recently worked with RISC-V vector instructions using these simulators: - **Spike (`riscv-isa-sim`)** - https://github.com/riscv-software-src/riscv-isa-sim - Supports V-Ext. (v2.0) and P-Ext. (v0.9.2) - No pre-build binaries available - Need to compile simulator (`spike`) and proxy kernel (`pk`) from source - Debugging support with GDB very limited - **riscvOVPSimPlus** - https://www.ovpworld.org/library/wikka.php?wakka=riscvOVPsimPlus - Version with V-Ext. support: Sign-up required for download, internet connection for usage - However, perfomance and usability is great (Much faster than Spike) Both of them are only ISS, e.g. not cycle accurate, but that should not be an issue. --- Another thing I would like to point out is that the vectorization support in the RISC-V GCC toolchain seems to be (References: [1](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/975) [2](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/990) [3](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/968)). Thus, one should switch to using LLVM/Clang instead (LLVM also supports all RVV intrinsics). -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
