[tvm] branch main updated: [USMP] Change internal workspace section (#11246)

[mousius]

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mousius pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/tvm.git


The following commit(s) were added to refs/heads/main by this push:
     new 3911b85ed7 [USMP] Change internal workspace section (#11246)
3911b85ed7 is described below

commit 3911b85ed7b95a9fc4352e4b16d58fd9cfce497a
Author: Manupa Karunaratne <manupa.karunara...@arm.com>
AuthorDate: Mon May 9 21:10:23 2022 +0100

    [USMP] Change internal workspace section (#11246)
    
    This commit changes the internal workspace generation
    to be under .bss.noinit.* with NOLOAD behaviour as it
    does not need any form initialization.
---
 apps/microtvm/cmsisnn/corstone300.ld  | 6 +++---
 apps/microtvm/ethosu/corstone300.ld   | 6 +++---
 src/target/source/source_module.cc    | 2 +-
 tests/python/relay/aot/corstone300.ld | 6 +++---
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/apps/microtvm/cmsisnn/corstone300.ld 
b/apps/microtvm/cmsisnn/corstone300.ld
index 1d2dd88057..e52b23da33 100644
--- a/apps/microtvm/cmsisnn/corstone300.ld
+++ b/apps/microtvm/cmsisnn/corstone300.ld
@@ -247,12 +247,12 @@ SECTIONS
 
   } > DTCM
 
-  .bss.NoInit :
+  .bss.noinit (NOLOAD):
   {
     . = ALIGN(16);
-    *(.bss.NoInit)
+    *(.bss.noinit.*)
     . = ALIGN(16);
-  } > DDR AT > DDR
+  } > SRAM AT > SRAM
 
   .bss :
   {
diff --git a/apps/microtvm/ethosu/corstone300.ld 
b/apps/microtvm/ethosu/corstone300.ld
index 3f36f218cb..fb670d45c9 100644
--- a/apps/microtvm/ethosu/corstone300.ld
+++ b/apps/microtvm/ethosu/corstone300.ld
@@ -251,12 +251,12 @@ SECTIONS
 
   } > DTCM
 
-  .bss.NoInit :
+  .bss.noinit (NOLOAD):
   {
     . = ALIGN(16);
-    *(.bss.NoInit)
+    *(.bss.noinit.*)
     . = ALIGN(16);
-  } > DDR AT > DDR
+  } > SRAM AT > SRAM
 
   .bss :
   {
diff --git a/src/target/source/source_module.cc 
b/src/target/source/source_module.cc
index 046b7e9606..11ff409e1d 100644
--- a/src/target/source/source_module.cc
+++ b/src/target/source/source_module.cc
@@ -242,7 +242,7 @@ class CSourceCrtMetadataModuleNode : public 
runtime::ModuleNode {
       for (const auto& kv : metadata_->pool_inputs.value()) {
         tir::usmp::AllocatedPoolInfo allocated_pool_info = kv.second;
         if (allocated_pool_info->pool_info->is_internal) {
-          code_ << "__attribute__((section(\".data.tvm\"), ";
+          code_ << "__attribute__((section(\".bss.noinit.tvm\"), ";
           code_ << "aligned(" << 16 << ")))\n";
           code_ << "static uint8_t " << 
allocated_pool_info->pool_info->pool_name << "["
                 << allocated_pool_info->allocated_size->value << "];\n";
diff --git a/tests/python/relay/aot/corstone300.ld 
b/tests/python/relay/aot/corstone300.ld
index a825da74c1..bee82a9843 100644
--- a/tests/python/relay/aot/corstone300.ld
+++ b/tests/python/relay/aot/corstone300.ld
@@ -251,12 +251,12 @@ SECTIONS
     . = ALIGN(16);
   } > SRAM AT > SRAM
 
-  .bss.NoInit :
+  .bss.noinit (NOLOAD):
   {
     . = ALIGN(16);
-    *(.bss.NoInit)
+    *(.bss.noinit.*)
     . = ALIGN(16);
-  } > DDR AT > DDR
+  } > SRAM AT > SRAM
 
   .bss :
   {