cbalint13 commented on issue #11260:
URL: https://github.com/apache/tvm/issues/11260#issuecomment-1144927868
@MichaelJKlaiber ,
This is really great work, congratulations !
Watching with interest this ntiative, allow me to ask questions towards
***100% out-of-tree*** functionality.
#### Case usage:
----
Given the case of a custom risc-v (or any llvm cpu) ISA extension (i.e.
[custom HW/ISA](https://github.com/cbalint13/OLIMP) that itself can
change&autotunne):
* Currently (without UMA) it is necessary to **fork & insert** into TVM
codebase:
1. new strategies:
```python/tvm/relay/op/strategy/__init__.py```
```python/tvm/relay/op/strategy/olimp.py```
2. new target:
```python/tvm/target/__init__.py```
```python/tvm/target/target.py```
3. some new topi that includes (auto)tensorization:
```python/tvm/topi/olimp/__init__.py```
```python/tvm/topi/olimp/conv2d.py```
```python/tvm/topi/olimp/dense.py```
```python/tvm/topi/olimp/injective.py```
```python/tvm/topi/olimp/tensor_intrin.py```
Now after these **"C" code & binary libs** can be emmited that include
**inline asm calls** with tensorized custom ISA.
All **operators not covered** by declared **new strategies** defaults to
**"the generic tvm"** not taking custom ISA advantage.
----
#### Now the questions:
* Will UMA permit such workflow **without touching** and maintain a separate
TVM fork / codebase ?
* [UMA
RFC](https://github.com/apache/tvm-rfcs/blob/main/rfcs/0060_UMA_Unified_Modular_Accelerator_Interface.md)
tells to register a UMA (with nice class properties overrides) will all this
be possible **100% out-of tree** ?
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