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from 57a3b26343 [Fix] Fix `dtype` in Cache-Read/Write (#12421)
add e3d0305881 [TIR] Avoid `import *` in TIR tensor intrinsic registration
(#12424)
add e111984117 [TIR] Allow `tir.Buffer` converted to
`BufferLoad/BufferRegion` with `__getitem__` (#12422)
No new revisions were added by this update.
Summary of changes:
python/tvm/meta_schedule/default_config.py | 2 +-
python/tvm/meta_schedule/testing/schedule_rule.py | 6 ++--
python/tvm/tir/buffer.py | 41 ++++++++++++++++++++--
python/tvm/tir/tensor_intrin/__init__.py | 6 +---
python/tvm/tir/tensor_intrin/arm_cpu.py | 1 +
.../test_meta_schedule_auto_tensorize.py | 9 ++---
...est_meta_schedule_postproc_rewrite_tensorize.py | 2 +-
...ta_schedule_schedule_rule_multi_level_tiling.py | 4 +--
.../unittest/test_meta_schedule_tune_relay.py | 8 ++---
tests/python/unittest/test_target_codegen_llvm.py | 15 ++++----
.../python/unittest/test_tir_schedule_tensorize.py | 11 +++---
11 files changed, 71 insertions(+), 34 deletions(-)
