This is an automated email from the ASF dual-hosted git repository.
github-bot pushed a change to branch last-successful
in repository https://gitbox.apache.org/repos/asf/tvm.git
from fb073510b6 [MetaSchedule] Handle deserializing empty string RVs in
trace (#12481)
add 436c17f885 [HEXAGON][TOPI] This PR adjusts schedules so >64 length
vector loads/stores are not generated at LLVM level. This is a workaround for
an instruction selection issue in current version of llvm for hexagon (#12471)
add e140a27495 [COMMUNITY] Adam Straw -> Reviewer (#12480)
add aa97f4afb5 [TIR] Disallow vectorization with strides in VerifyGPUCode
(#12477)
No new revisions were added by this update.
Summary of changes:
CONTRIBUTORS.md | 1 +
python/tvm/topi/hexagon/slice_ops/cast.py | 6 ++--
src/target/source/codegen_cuda.cc | 1 +
src/tir/analysis/verify_gpu_code.cc | 17 ++++++++++
.../contrib/test_hexagon/topi/test_cast_slice.py | 4 +--
.../unittest/test_tir_analysis_verify_gpu_code.py | 37 ++++++++++++++++------
6 files changed, 53 insertions(+), 13 deletions(-)
