guberti commented on code in PR #12448:
URL: https://github.com/apache/tvm/pull/12448#discussion_r951569635
##########
python/tvm/relay/op/strategy/arm_cpu.py:
##########
@@ -239,6 +239,29 @@ def conv2d_strategy_arm_cpu(attrs, inputs, out_type,
target):
wrap_topi_schedule(topi.arm_cpu.schedule_depthwise_conv2d_nhwc),
name="depthwise_conv2d_nhwc.arm_cpu",
)
+
+ # Optimized special case depthwiseConv2D operation. Requires a 3x3
kernel, a
+ # NHWC layout, a HWOI kernel layout (which we would ideally
rearrange), no dilation,
+ # "SAME" padding, int8 inputs and outputs, the same number of
input and output
+ # channels, and for that channel count to be divisible by 4.
+ #
+ # Additional work could remove some of these restrictions.
+
+ elif (
+ isa.has_dsp_support
+ and kernel.shape[0] == kernel.shape[1] == 3
+ and dilation_w == dilation_h == 1
+ and kernel.shape[3] == 1
+ and data.dtype == "int8" # channel_multiplier == 1
Review Comment:
Sorry, it should be on the above line. Fixed!
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