shingjan opened a new pull request, #12668:
URL: https://github.com/apache/tvm/pull/12668
This PR intends to fix the CUDA auto-inline schedule rule while processing
TIR block with one single constant consumer block.
Before this PR, the TIR added in the test will throw the following error
while being auto-inlined as it shouldn't be auto-inlined according to the rule.:
```
E ScheduleError: An error occurred in the schedule primitive
'compute-inline'.
E The IR with diagnostic is:
E # from tvm.script import tir as T
E @tvm.script.ir_module
E class Module:
E @T.prim_func
E def main(T_full: T.Buffer[(1, 12, 4096), "int64"]) -> None:
E # function attr dict
E T.func_attr({"global_symbol": "main", "tir.noalias":
True})
E # body
E # with T.block("root")
E for i0, i1, i2 in T.grid(1, 12, 4096):
E # tir.Block#0
E with T.block("T_full"):
E ^^^^^^^^^^^^^^^^^^^^^^^
E ax0, ax1, ax2 = T.axis.remap("SSS", [i0, i1, i2])
E T.reads()
E T.writes(T_full[ax0, ax1, ax2])
E T_full[ax0, ax1, ax2] = T.int64(0)
E
E Error message: The block tir.Block#0 is an output block
```
Models that is impacted by this fix: `vision_maskrcnn` & `hf_Reformer`
cc: @zxybazh @junrushao @vinx13
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