guberti commented on code in PR #12448:
URL: https://github.com/apache/tvm/pull/12448#discussion_r961896851
##########
tests/python/relay/strategy/arm_cpu/test_depthwise_conv2d.py:
##########
@@ -147,5 +147,30 @@ class
TestDepthwiseConv2d_NHWC_HWOI(BasicDepthwiseConv2dTests):
schedule_name = tvm.testing.parameter("depthwise_conv2d_nhwc.generic")
+class TestDepthwiseConv2d_NHWC_HWOI_DSP(BasicDepthwiseConv2dTests):
+ """This test is for depthwise_conv2d_nhwc_dsp.arm_cpu schedule."""
+
+ data_shape, kernel_size, num_filter, strides, padding, dilation =
tvm.testing.parameters(
+ # The LLVM implementation doesn't support "SAME" and "VALID" padding,
+ # so padding must be explicitly specified.
+ # Depthwise_conv2d parameters from MobileNetV1 0.25x
+ ((1, 48, 48, 8), (3, 3), 8, (1, 1), 1, 1),
+ ((1, 48, 48, 16), (3, 3), 16, (2, 2), (1, 1, 0, 0), 1),
+ ((1, 24, 24, 32), (3, 3), 32, (1, 1), 1, 1),
+ ((1, 24, 24, 32), (3, 3), 32, (2, 2), (1, 1, 0, 0), 1),
+ ((1, 12, 12, 64), (3, 3), 64, (1, 1), 1, 1),
+ ((1, 12, 12, 64), (3, 3), 64, (2, 2), (1, 1, 0, 0), 1),
+ ((1, 6, 6, 128), (3, 3), 128, (1, 1), 1, 1),
+ ((1, 6, 6, 128), (3, 3), 128, (2, 2), (1, 1, 0, 0), 1),
+ ((1, 3, 3, 256), (3, 3), 256, (1, 1), 1, 1),
+ # Asymmetric height and width
+ ((1, 25, 5, 64), (3, 3), 64, (1, 1), 1, 1),
+ )
+ data_layout = tvm.testing.parameter("NHWC")
+ dtype = tvm.testing.parameter("int8")
+ kernel_layout = tvm.testing.parameter("HWOI")
+ schedule_name = tvm.testing.parameter("depthwise_conv2d_nhwc_dsp.arm_cpu")
Review Comment:
Unfortunately, we don't have infrastructure to test invalid cases :(. It's
definitely worth addressing in a future PR, though.
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